Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-20
2001-11-13
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S592000, C438S664000
Reexamination Certificate
active
06316319
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing high density semiconductor devices having shallow junctions. The present invention is particularly applicable in manufacturing high density CMOS semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interleaved dielectric and conductive layers formed thereon. In a conventional semiconductor device
100
illustrated in
FIG. 1
, substrate
1
is provided with field oxide
2
for isolating an active region comprising source/drain regions
3
, and a gate electrode
4
, typically of doped polysilicon, above the semiconductor substrate with gate oxide
5
therebetween. Interlayer dielectric layer
6
, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer
8
, and source/drain regions
3
through contacts
7
, and to transistor gate electrode
49
. Dielectric layer
9
, typically silicon dioxide, is deposited on conductive layer
8
, and another conductive layer
10
, typically aluminum or an aluminum-base alloy, formed on dielectric layer
9
and electrically connected to conductive layer
8
through vias
11
.
With continued reference to
FIG. 1
, conductive layer
10
is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer
12
, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer
13
deposited thereon. Protective dielectric layer
13
typically comprises a nitride layer, such as silicon nitride (Si
3
N
4
). Alternatively, protective dielectric layer
13
may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer
13
provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer
13
, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer
10
for external connection by means of bonding pad
14
and electrically conductive wires
15
or an external connection electrode (not shown).
Although only two conductive layers
8
and
10
are depicted in
FIG. 1
for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g., five conductive metal layers. Also in the interest of illustrative convenience,
FIG. 1
does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, it becomes necessary to decrease the depth of the source and drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate electrode having a width of about 0.25 microns, the junction depth (X
J
) should be no greater than about 800 Å. This objective is extremely difficult to achieve, particularly when implanting impurities to dope the gate electrode and form source/drain regions.
For example, conventional semiconductor methodology comprises doping polysilicon gate electrode
4
and forming source/drain regions
3
in the same ion implantation. That is, the ion implantation to form source/drain regions
3
also functions to dope polysilicon gate electrode
4
. However, in order to achieve shallow source/drain junctions, the implantation energy for forming source/drain regions
3
is relatively low. The implanted impurities achieve desirably shallow penetration in substrate
1
at the expense of shallow penetration in gate electrode
4
. This causes gate depletion, i.e., lack of carriers at the gate electrode/gate oxide interface, resulting in decreased capacitance and reduced drive current.
Ion implantation can be performed at higher energy levels to reduce gate depletion. However, after activation annealing, the resulting source/drain regions extend considerably beyond the targeted maximum X
J
of about 800 Å. An undesirably deep Xi can cause short channel effects, generating a leakage current which degrades the performance of the semiconductor device.
SUMMARY OF THE INVENTION
There exists a need exists for a method of manufacturing a semiconductor device having shallow junctions and adequately doped gate electrodes.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device. The method includes forming a dielectric layer on an upper surface of a semiconductor substrate and forming a silicon layer on the dielectric layer. The method also includes patterning the silicon layer to form a gate electrode having an upper surface and side surfaces and implanting impurities, using the gate electrode as a mask, to form source/drain extension implants in the semiconductor substrate. The method further includes depositing and etching an insulating layer to form sidewall spacers on the side surfaces of the gate electrode. Additionally, the method includes depositing a metal on the semiconductor device and reacting the metal with silicon in the gate electrode and in the semiconductor substrate to form a metal-silicide layer on the gate electrode and on the semiconductor substrate, before activation annealing the source/drain extension implants.
Another aspect of the present invention is a method of manufacturing a semiconductor device that includes forming a dielectric layer on an upper surface of a monocrystalline semiconductor substrate, forming a polycrystalline silicon layer on the dielectric layer and patterning the silicon layer to form a gate electrode. The method also includes implanting impurities to form source/drain extension implants in the semiconductor substrate, depositing an insulating layer and etching the insulating layer to form sidewall spacers on the side surfaces of the gate electrode. The method further includes forming a film having a first thickness over the gate electrode and a second thickness over the semiconductor substrate and implanting impurities to form moderately or heavily doped implants in the semiconductor substrate and to dope the gate electrode.
Other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5956584 (1999-09-01), Wu
patent: 6087234 (2000-07-01), Wu
Ishida Emi
Ju Dong-Hyuk
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Thomas Toniae M.
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