Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-01-06
2001-02-13
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S680000
Reexamination Certificate
active
06187622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and a method for producing the same. More particularly, the present invention relates to the construction of a DRAM (Dynamic Random Access Memory) employing a material having a high dielectric constant for the capacitor insulation film, and a method for producing the same.
2. Description of Prior Art
The DRAM has been widely used as a semiconductor memory device which is capable of random input and output of stored information. A DRAM generally has a memory cell array which is a storage area for storing much information and a peripheral circuit required for external input/output.
The memory cell array which occupies a large area on a semiconductor chip comprises a plurality of memory cells, each storing unit information, arranged in a matrix. One memory cell generally comprises one MOS (Metal Oxide Semiconductor) transistor and a capacitor connected thereto. A memory cell of this type is called 1-transistor, 1-capacitor memory cell. Because of simple construction, a memory cell of this type allows an increased degree of integration of the memory cell array. Thus it has been widely used for DRAMs of large storing capacities.
Memory cells of DRAM can be classified into several types based on the capacitor construction used. Among these is one called a stacked capacitor. The stacked capacitor increases the area of electrodes opposing each other by extending a key portion of the capacitor onto a gate electrode or a field oxide film.
The stacked capacitor having such a feature as described above can secure a capacitance even when the element is made extremely small due to the integration of semiconductor memory device. As a result, stacked capacitors have come to be used widely as semiconductor memory devices become highly integrated.
However, in such applications that require even smaller elements as in 256 M bit DRAM, for example, it becomes difficult to provide the required value of capacitance even with the stacked capacitor.
Thus attempts to increase the capacitance have been made by using a dielectric film made of a material having high dielectric constant such as PZT (lead titanate zirconate) as the capacitor insulation film. For example, FIG. 8 of Japanese Patent Kokai Publication No. 7-142598 shows an example of DRAM employing a material having high dielectric constant such as PZT as the capacitor insulation film. FIG. 1 of the publication shows a capacitor lower electrode having a separation width (slot width) of 0.2 &mgr;m and height of 150 nm.
According to this example, a capacitor insulation film of a high dielectric constant is formed by a known method of deposition on the capacitor lower electrode processed with a separation width of 0.2 &mgr;m or less, then an upper electrode is formed by MOCVD process.
However, methods of the prior art have such problems as described below. That is, in the prior art, attempts have been made to make lower electrodes called the stacked capacitor in a 3-dimensional configuration in order to store a required amount of electric charge in a capacitor which is electrically connected to a principal plane of a semiconductor substrate via an aperture of an inter-layer insulation film. While this results in a separation width between adjacent lower electrodes as small as 0.2 &mgr;m or less and the area of the lower electrode itself projected onto a principle plane as small as 0.15 square micrometers or less, thus requiring it to secure a required facing area of the electrodes by increasing the height of the lower electrode thereby storing the required amount of electric charge in the capacitor, in a DRAM having a storage capacity of 1 G bit, for example. During the producing process, however, adjacent lower electrodes are separated by a very narrow and deep slot and therefore the upper electrode of the capacitor to be provided on the lower electrode must be formed over a step which is even more narrow and deep in correspondence to the thickness of the insulation film, even when the capacitor insulation film can be formed uniformly over the lower electrodes of such a configuration. Thus the capacitor insulation film cannot be fully covered by the upper electrode in simple MOCVD process or sputtering method, resulting in such a problem as a portion where the upper electrode is not formed remains. Hence there has been a limitation on the effort of providing a required value of capacitance while maintaining the reliability of the device.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problems described above. An object of the present invention is to provide a semiconductor memory device which is capable of securing a specified value of capacitance even when the elements are made extremely small for higher degree of integration. Another object of the present invention is to provide a method of producing the semiconductor memory device which secures a specified value of capacitance while maintaining the reliability of the device.
A semiconductor memory device according to first configuration of the present invention is provided with a semiconductor substrate which has a principal plane, an inter-layer insulation film which is formed on the principal plane of the semiconductor substrate and has such an aperture that reaches the principal plane of the semiconductor substrate, a connecting member embedded in the aperture, a plurality of capacitor lower electrodes arranged side by side while being separated by slots and electrically connected to the principal plane of the semiconductor substrate via the connecting member, a capacitor insulation film formed from a material having a high dielectric constant to cover the lower electrodes while leaving a portion of the slot as a step, and a capacitor upper electrode formed on the capacitor insulation film, wherein the adjacent capacitor lower electrodes are separated by a space of 0.2 &mgr;m or less, ratio of the height of the lower electrode to the separation width being 1 or higher, and the capacitor upper electrode is formed to cover the capacitor insulation film and fill the step.
According to the first configuration of the present invention, such a problem as a failure of forming the capacitor upper electrode in the step portion leading to lower reliability of the device can be eliminated, and the specified value of capacitance can be obtained even when the elements are made extremely small due to high degree of integration.
A semiconductor memory device according to second configuration of the present invention is provided with a semiconductor substrate which has a principal plane, an inter-layer insulation film which is formed on the principal plane of the semiconductor substrate and has such an aperture that reaches the principal plane of the semiconductor substrate, a connecting member embedded in the aperture, a plurality of capacitor lower electrodes arranged side by side while being separated by slots and electrically connected to the principal plane of the semiconductor substrate via the connecting member, a capacitor insulation film formed from a material having a high dielectric constant to cover the capacitor lower electrode while leaving a portion of the slot as a step, and a capacitor upper electrode formed in plasma which includes etchable gas to cover the capacitor insulation film and fill the step.
According to the second configuration of the present invention,even a very narrow and deep step can be effectively filled, and such a problem as a failure of forming the capacitor upper electrode in the step portion leading to lower reliability of the device can be eliminated, while the specified value of capacitance can be obtained even when the elements are made extremely small due to high degree of integration.
A semiconductor memory device according to third configuration of the present invention is, in addition to the second configuration, separation width of the adjacent capacitor lower electrodes is 0.2 &mgr;m or less, and the ratio of the h
Horikawa Tsuyoshi
Kuroiwa Takeharu
Makita Tetsuro
Mikami Noboru
Chaudhari Chandra
Mitsubishi Denki & Kabushiki Kaisha
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