Method of tilted implant for pocket, halo and source/drain...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S525000, C438S306000

Reexamination Certificate

active

06190980

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for overcoming the process limit, due to shading effects in dense structures, of using large angle tilted implant techniques in ULSI circuits.
BACKGROUND OF THE INVENTION
Large angle titled implant (“LATI”) of either pocket, halo or source/drain extensions is currently needed in ultra large scale integrated (“ULSI”) complimentary metal oxide semiconductor (“CMOS”) transistors in order to suppress “short-channel effects.” Short channel effects are described in further detail in application Ser. No. 09/122,815, filed on Jul. 27, 1998, entitled MOS TRANSISTOR WITH HIGH-K SPACER DESIGNED FOR ULTRA-LARGE SCALE INTEGRATION, commonly assigned to the assignee of record for the present application, the contents of which are incorporated herein by reference.
Limitations exist, however, of applying LATI techniques in ULSI circuits. For example, due to the very high packing density of a ULSI circuit, shadowing effects from both the gate stack and photo-resist layers restricts the maximum tilt angle that can be used for ion implantation. Presently, the largest tilt angle used commercially for implants is illustrated schematically in FIG.
1
. As shown in
FIG. 1
, the two angles &thgr;
1
, &thgr;
2
corresponding to the shadowing effect from gate stacks and photo-resist layers, respectively, can be expressed according to the following equation:
&thgr;
MAX
=min(&thgr;
1
&thgr;
2
)
As can be seen, the maximum tilt angle, &thgr;
max
, is dependent upon the gate stack height A and the thickness of the photo-resist layer B. This maximum angle of implantation, however, is smaller than what a device engineer currently may desire in the fabrication of ULSI circuits, which is typically larger than 40°.
Another limitation of applying LATI techniques in ULSI circuits is that the largest angle allowable for implants is impacted by the random variation of several process parameters. These parameters include for example gate critical dimensions, the thickness of a gate stack and the thickness of the photo-resist layer. Lithography overlay may also have a significant impact. In a worst case scenario of lithography overlay, therefore, the available &thgr;
MAX
could ultimately be very small.
What is lacking in the art is a small angle tilted implant technique that has the equivalent doping effect of large angle tilted implants. One advantage of the small angle tilted implant technique over the large angle tilted implant technique is the circumvention of the maximum angle limit (&thgr;
MAX
) that occurs in the large angle method. Another advantage to a small angle tilted implant technique would be self alignment of the pocket/halo/extension implant to the gate of the device.
BRIEF SUMMARY OF THE INVENTION
In view of the above, the present invention provides a method of performing tilted implantation in ULSI dense structures. According to the method of the invention, a substrate layer is provided and an oxide layer is deposited on top of the substrate layer. The oxide layer is selectively etched down to a level of substantially the substrate layer to provide a window opening in the oxide layer. Nitride spacers are then deposited within the window opening to define an actual gate window. Source, drain and gate implants can then be implanted at a small angle relative to the vertical direction (i.e., &thgr;
A
). Gate material is deposited to fill the actual gate window.
One advantage of the small angle tilted implant technique over the large angle tilted implant technique is the elimination or reduction of the maximum angle limit (&thgr;
MAX
) that occurs in the large angle method. Another advantage to the small angle tilted implant technique of the invention is the self alignment of the pocket/halo/extension implant to the gate of ULSI device.
These and other features an advantages of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention taken in conjunction with the appended drawings.


REFERENCES:
patent: 5399508 (1995-03-01), Nowak
patent: 5424229 (1995-06-01), Oyamatsu
patent: 5434093 (1995-07-01), Chau et al.
patent: 5943576 (1999-08-01), Kapoor
patent: 6008094 (1999-12-01), Krivokapic et al.
patent: 6025232 (2000-02-01), Wu et al.

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