Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-18
2001-12-18
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000
Reexamination Certificate
active
06331480
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method used to fabricate integrated circuits, on a semiconductor substrate, and more specifically to a method used to fabricate conductive wiring structures, embedded by low dielectric constant materials.
(2) Description of the Prior Art
To increase the performance of integrated circuits, fabricated on semiconductor substrates, in terms of metal conductivity, and insulator capacitance, copper is now being used to replace the higher resistivity aluminum, or tungsten, counterparts, for wiring applications, while low dielectric constant, (low K), materials, such as fluorine-doped silicon oxide glass, (FSG), hydrogen silsesquioxane, (HSQ), or aromatic hydrocarbons, with dielectric constants of about 2.5 to 3.5, are being used to replace chemically vapor deposited silicon oxide layer, which has a dielectric constant of about 4.0 to 4.5. The use of low K materials however, can present adhesion problems, when overlaid with higher dielectric constant materials, used as a hard mask for damascene type patterning procedures. For example a composite layer, damascene pattern, comprised of an overlying hard mask material, such as CVD silicon oxide, and an underlying low K material, such as FSG, is formed using conventional photolithographic and dry etching procedures. However the removal of the photoresist or polymer shape, used to define the damascene pattern, in the composite layer, can result in a loss of adhesion between the overlying hard mask, silicon oxide layer, and the underlying FSG layer, specifically during a wet stripping, or a wet clean up step, used after the photoresist stripping procedure. The loss of adhesion between these layers of the composite damascene mask can result in an inadequate, subsequent metal fill, exhibiting bridging to adjacent metal shapes, and leading to unwanted leakage and yield loss.
This invention will offer solutions for the loss of adhesion, between a silicon oxide hard mask, and an underlying low K material, that can occur during polymer, or photoresist removal procedures. Specific treatments, described in this invention, applied to a low K material, used as the underlying layer of a composite layer, damascene mask, or used as an interlevel dielectric layer, prior to the deposition of the hard mask material, results in an improvement of the adhesion between the overlying hard mask, and the underlying low K material. This invention will offer treatments featuring an NH
4
OH treatment, or a UV curing procedure, applied to an exposed low K material. Prior art, such as Joshi, in U.S. Pat. No. 4,732,801, describes a procedure to improve the adhesion of refractory metals, or silicon oxide layers, to underlying materials, but that prior art does not use the treatments described in this invention, nor does it describe the conditions needed for improving the adhesion of hard mask insulator layers, to underlying low K materials.
SUMMARY OF THE INVENTION
It is an object of this invention to create metal interconnect structures, and via plug structures, using a damascene procedure.
It is another object of this invention to use a low K material, as an underlying component of a composite layer, damascene mask pattern, comprised of an overlying hard mask layer, such as silicon oxide, and the underlying low K layer.
It is still another object of this invention to treat the underlying low K layer, of the composite layer, damascene mask pattern, with a NH
4
OH treatment, or with a UV curing procedure, prior to deposition of the overlying hard mask layer.
In accordance with the present invention a method of fabricating metal interconnect structures, using a damascene pattern mask, as an interlevel dielectric layer, and featuring improved adhesion between layers of chemical vapor deposited, (CVD), insulator layers, and underlying low K materials, has been developed. A first iteration comprises a metal plug structure, formed in a via hole in a first low K material, exposing an underlying metal interconnect structure. After deposition of a first CVD insulator layer a composite layer, damascene mask pattern, comprised of an overlying second CVD insulator layer, and an underlying second low K material, is formed on the top surface of the first CVD insulator layer. A NH
4
OH, or a UV treatment, is performed to the second low K material, of the composite layer, damascene mask pattern, prior to deposition of the second CVD insulator, to provide adhesion improvements, needed specifically during the wet procedure, used to remove the photoresist shape, used to define the damascene mask pattern. After removal of the portion of first CVD insulator, exposed in the damascene mask pattern, exposing the top surface of the metal plug, an overlying metal interconnect structure is formed in the opening, in the damascene mask pattern.
A second iteration of this invention features the use of the NH
4
OH, or UV treatment, applied to the first low K material, that is used as an interlevel dielectric layer, after the metal plug formation, and prior to deposition of the first CVD insulator layer. A damascene mask pattern, comprised of only a second CVD insulator layer, is next formed and used to accept an overlying interconnect structure.
A third iteration of this invention features the formation of a metal plug structure, formed in a first CVD insulator layer, contacting an underlying metal interconnect structure. A composite layer, damascene mask pattern, again comprised of an overlying second CVD insulator layer, and an underlying low K material, is used to accept the overlying metal interconnect structure, with the NH
4
OH, or UV treatment performed prior to the deposition of the second CVD insulator layer.
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Cheng Yao-Yi
Tao Hun-Jan
Tsai Chia-Shiung
Ackerman Stephen B.
Chaudhuri Olik
Peralta Ginette
Saile George O.
Taiwan Semiconductor Manufacturing Company
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