Method of fabricating interconnect lines and plate...

Details Method of fabricating interconnect lines and plate... Method of fabricating interconnect lines and plate...

1999-01-13

2001-02-06

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000

Reexamination Certificate

active

06184075

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is directed to a method of fabricating semiconductor devices. In particular, the invention is directed to a method of fabricating interconnect lines together with plate electrodes of a storage capacitor in a semiconductor device such as a semiconductor memory.
The chosen method of fabricating interconnect lines or wiring layers in a semiconductor device plays an important role in the production of semiconductor devices such as semiconductor memories (e.g., dynamic random access memories (DRAM), static random access memories (SRAM), etc.). The manner in which such interconnect lines are fabricated in the device may affect the processing speed and reliability of the device, as well as the manufacturing yield of the production.
With the constant pressure to achieve higher integration in semiconductor devices, especially in memory devices, the skilled artisan is required to forego the horizontal expansion of the integration across the base of the device in favor of vertical development. This increase in vertical integration of a semiconductor device typically involves applying multiple layers of integration, thus, leading to an increase in the aspect ratio (i.e., ratio of vertical height to the horizontal length) of the device. High aspect ratios lead to significant problems in the fabrication process. Each layer added to the design of the semiconductor device increases the complexity of and time delay in overall production time.
FIGS. 1A-5B
illustrate a conventional semiconductor device during fabrication having a relatively high aspect ratio (approximately 4.5-5.5). (For ease of illustration, among
FIGS. 1A-5B
, figures labeled with like numbers represent the semiconductor device during the same process step of fabrication. Figures having a suffix “A,” however, represent a cross-sectional view of the cell array portion of a conventional semiconductor memory device viewed along line “A—A” of
FIG. 5A
, whereas figures having a suffix “B,” represent a cross-sectional view of the peripheral circuit portion of the same semiconductor memory device viewed along line “B—B” of
FIG. 5B.
)
The conventional semiconductor memory device shown in
FIG. 1A
is fabricated with a source/drain region
2
and gate electrode
3
of a transistor formed on a semiconductor substrate
1
. Over the electrode region
3
an inter layer dielectric (ILD) is patterned having bit lines
4
formed as shown in
FIG. 1B. A
storage electrode
5
(
FIG. 1A
) is patterned in and above the ILD. A dielectric film
6
is deposited over the storage electrode
5
, together with a plate electrode
7
. The dielectric film
6
and electrode
7
are patterned to complete a storage cell capacitor for the memory cell in the cell array of the semiconductor memory device.
A planarization layer
8
(
FIG. 2A
) is used to planarize the step coverage produced by the fabrication process. Material such as O
3
-TEOS (tetra ethoxy silane) is typically used and deposited to a thickness of 3000-7000 A (angstroms). An insulation layer
9
, typically made of PE-TEOS (plasma enhanced-tetra ethoxy silane), is deposited to a thickness of 1000-3000 A. A layer of photoresist
10
is then formed and patterned to allow for the formation of a contact hole in the peripheral portion of the semiconductor device, as shown in FIG.
2
B. As shown in
FIGS. 3A and 3B
, the semiconductor device is then exposed to an isotropic-etching process step that etches insulation layer
9
and planarization layer
8
to a depth of 1000-4000 A. The remainder of the planarization layer
8
and ILD are then etched using an anisotropic-etching process to form contact hole
11
over source/drain region
2
(FIG.
3
B).
Tungsten is deposited in the contact hole
11
and on the top surface of the semiconductor device to a thickness of 2000-5000 A to form a conductive layer
12
. This layer is patterned to form interconnect line
12
in the peripheral portion of the semiconductor device, as shown in FIG.
4
B.
FIGS. 5A and 5B
show mask works used during the fabrication process to form the various layers of the cell array portion and the peripheral portion, respectively, of the semiconductor memory device. As shown in
FIG. 5A
, a gate electrode mask
3
′, a bit line mask
4
′, a storage electrode mask
5
′, and a plate electrode mask
7
′ are respectively used to form the gate electrode
3
, bit line
4
, storage electrode
5
, and plate electrode
7
of the cell array portion of the semiconductor device. Similarly, in
FIG. 5B
, gate electrode mask
3
′, bit line mask
4
′, contact hole mask
11
′, and interconnect line mask
12
′ are respectively used to form the gate electrode
3
, bit line
4
, contact hole
11
, and interconnect line
12
of the peripheral portion of the semiconductor device.
As can be seen from the above brief description of the fabrication process for a conventional semiconductor device, a semiconductor device, such as a memory device, having high integration requires a multitude of layers. Any increase in integration, for example, adding interconnect lines or wiring layers, would increase the aspect ratio. As the aspect ratio increases, the problems in fabrication and reliability of the device increase. For example, because the contact hole
11
(
FIG. 3B
) is so deep (i.e., 1.2 microns), the gas used to etch the contact hole in the anisotropic-etching process step cannot react properly with the oxide layer at the bottom of the contact hole. As a result, the metal contact necessary for the reliable operation of the semiconductor device is inferior. Furthermore, such an increase in the number of layers causes significant delays in the overall production of the semiconductor devices as each new layer adds one or more steps to the overall fabrication process, thus, further complicating and delaying the manufacture of the devices.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method that permits the increase of integration of semiconductor devices without a corresponding increase in the aspect ratio of the devices.
It is an object of the invention to provide a method that allows fabrication of highly integrated semiconductor devices without further complicating or delaying the fabrication process.
The present invention accomplishes the above and other objects and advantages by providing a method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.
Using the present invention, the high levels of integration desired in semiconductor devices can be achieved without increasing the aspect ratio and without adding complex, time-consuming, and costly process steps to the overall fabrication process. As a result, the contact inferiority and unreliability found in highly integrated semiconductor devices having high aspect ratios produced in accordance with conventional fabrication processes can be obviated. In addition, because the conductive layer of the semiconductor device fabricated in accordance with the present invention functions as the plate electrode of the storage capacitor in the cell array portion of the memory device, as well as functioning as the interconnect layer in the peripheral portion of the device, the added wiring layer does not require a separate patterning process step. The increase in integration therefore does not require an accompanying increase in process steps and corresponding process delays.


REFERENCES:
patent: 5079670 (1992-01-01), Tigelaar et al.
patent: 5580813 (1996-12-01), Hachisuka et al.
patent: 5604365 (1997-02-01), Kajigaya

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