Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-29
2001-02-13
De Cady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C324S765010
Reexamination Certificate
active
06189120
ABSTRACT:
TECHNICAL FIELD
This invention relates to systems for testing circuitry. More particularly, the invention relates to burn-in testing. The invention also relates to methods for conducting such tests.
BACKGROUND OF THE INVENTION
Processed semiconductor wafers typically comprise an array of substantially isolated integrated circuitry which are individually referred to as “die” or “chips.” Some circuits are formed on boards, such as printed circuit boards, such as where the cost of designing and manufacturing an integrated circuit chip is too high relative to the size benefit. These chips or boards define various circuits for use in computers (e.g., video cards, sound cards, modem cards, etc.), televisions, telephone systems, and many other electronic devices. The chips or cards also define the finished circuitry components of, for example, processors and memory circuits. Common types of memory circuits are DRAM and SRAM chips.
After a semiconductor wafer has been fabricated, not all chips provided on the wafer prove operable, typically resulting in less than 100% yield. Accordingly, individual dies must be tested for functionality. The typical test procedure for DRAM or SRAM circuitry is to first access the device via bonding pads on the individual die. Thereafter, the wafer is subjected to test probing whereby the individual die are tested for satisfactory operation. Inoperable die are typically marked by an ink mark. After testing, the wafer is cut into individual die. The operable, non-marked die are collected.
The operable individual die are then assembled in final packages of either ceramic or plastic to define a packaged integrated circuit or device. After packaging, the integrated circuits are loaded into burn-in boards which comprise printed circuit boards having individual sockets. The burn-in boards are placed into a burn-in oven, and the parts are subjected to burn-in testing during which the die are operated for a period of time at different temperature cycles, including higher than operating temperatures. The dies are stressed to accelerate their lives in an effort to identify the weak die which are likely to degrade and fail under these tests. Manufacturers predict early failures, known as “infant mortalities”, to occur within a predetermined period of time of the burn-in cycle. Burn-in testing is typically conducted for a period of time sufficient to reveal these infant mortalities. For example, if infant mortalities are expected to occur within twenty-four or forty-eight hours of burn-in testing, the burn-in tests can be completed within such time periods. In this manner, semiconductor wafer manufacturers can effectively test the quality of their integrated circuits in a reasonable time frame prior to shipping the integrated circuits to consumers.
More particularly, the failure rate for a semiconductor device as a function of time generally follows what is known as a “bathtub-type curve”. The initial or infant mortality failure rate for die is very high at the start, and flattens out to near zero during a mid-time period, such as from one month through a period of 10 to 12 years, and then goes back up. In other words, if the integrated circuit survives the first one to five months or so of operation, it is highly probable that it will provide flawless operation through the tenth or twelfth year. Thereafter, usually after the expected lifetime of the device, material or other changes in the die cause the failure rate to increase exponentially, thus providing the bathtub shaped curve.
Burn-in testing can be conducted in either what is known as the static method or by a dynamic method. In both, the packaged die is electrically stressed under elevated temperature (e.g., 125° C.) for a given period of time (e.g., 24 hours) sufficient to test the die. Under a static electrical test, the die is subjected to an operating voltage that is much higher than the normal operating voltage. For example, the V
cc
node of the die may be subjected to an operating voltage of seven volts instead of the normal V
cc
voltage of three to five volts, while the V
ss
node of the die is held at ground. Operability is determined at the end of the test.
Under dynamic testing, individual devices are exercised on and off throughout the bum-in period, and the die is constantly monitored. Operability is determined during the test.
On a bum-in board, several receptacles are provided on a burn-in board (e.g., two feet by three feet in size), and the individual packages are received. Wiring extends from these individual receptacles/devices to one edge of the board where they connect outwardly to the testing and intelligence cycling circuitry. These long lengths of line create undesired parasitics such as unwanted noise, capacitance, resistance, inductance and crosstalk.
As described above, the die are subjected to a preliminary wafer-level test before sawing into individual die, and a burn-in test after separating and packaging of the individual die. Each of these two separate tests require some physical connection with a testing apparatus. During the wafer-level test probes are employed to directly contact bonding pads. During the burn-in testing, each individual chip is inserted into a socket on a burn-in board for the test.
Attention is directed to commonly assigned U.S. patent application Ser. No. 07/979,607, filed Nov. 20, 1992, now U.S. Pat. No. 6,058,497, titled “Testing and Burn-In of IC chips Using Radio Frequency Transmission,” which is incorporated herein by reference.
SUMMARY OF THE INVENTION
The invention provides a system and method for preliminary wafer-level testing and burn-in testing without physically contacting the semiconductor wafer or individual die.
In accordance with one aspect of the invention, a contactless method of burn-in testing semiconductor devices is provided wherein a burn-in board is equipped with an RF transmitter/receiver. Another transmitter/receiver is provided remote of a burn-in furnace such that test logic can be sent via radio frequency to each individual burn-in board during burn-in tests. The burn-in board has separate power lines for the V
cc
and V
ss
node connections to the respective semiconductor devices.
One aspect of the invention provides a burn-in testing method and system for evaluating a circuit under test. A burn-in board has a plurality of receptacles. At least one of the receptacles is sized to receive the circuit under test. Test interface circuitry is supported by the board and coupled to the receptacles. The test interface circuitry includes a transmitter and receiver. Power conductors are supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing. A burn-in oven has a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment. An interrogator unit has a. radio communication range extending to the test interface circuitry. The interrogator unit is configured to send commands to the test interface circuitry to exercise the circuit under test via radio communication and to receive responses to the commands via radio communication.
In one aspect of the invention, the test interface circuitry is mounted to the board. The power conductors comprise conductive traces formed on the board. Conductive traces formed on the board couple the receptacles to the test interface circuitry.
In one aspect of the invention, the interrogator unit is configured to provide an identification code as part of the interrogating information. The test interface circuitry includes ID labels assigned to respective receptacles, and the test interface circuitry is configured to compare the identification code provided by the interrogator unit with the ID label of the receptacle for the circuit under test, the test interface circuitry being configured to test cycle the operational circuitry when the identification code matches the ID label. The test interface circuitry is separately coupled to the respective receptacles suc
Cady Albert De
Lamarre Guy
Micro)n Technology, Inc.
Wells, St. John, Roberts, Gregory & Matking P.S.
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