Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-02
2001-03-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S229000, C438S230000
Reexamination Certificate
active
06207482
ABSTRACT:
BACKGROUNG OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a new method or sequence for the pocket implantation of deep sub-micron dual gate transistors.
(2) Description of the Prior Art
The continuing trend in the semiconductor industry is for smaller and faster devices that are created at constant or lower cost. These devices can essentially be broken down in bipolar devices and Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices where the latter category forms an increasing percentage of the total number of devices that are used in Integrated Circuit (IC) applications. It is projected that by the year 2000 the MOSFET devices will constitute roughly 90% of the overall market whereas the bipolar devices will be used for the remaining 10% of the applications. With reductions in device size is required a reduction in device power consumption which imposes the requirement of decreased device feature lengths. As a general rule can it be stated that device speed varies inversely with device feature length while power consumption increases approximately with the square of the device feature length. Feature size currently being approached is in the micron and sub-micron or 0.5 um range where it is not considered impossible that the feature size of 0.2 um will become a reality in the near future.
Field Effect Transistors (FET's) are at this time used extensively in Ultra Large-Scale Integration (ULSI) applications. FET's are formed using gate electrodes, usually made of polysilicon, and adjacent source/drain regions to which self-aligned source/drain contact areas are established. In its basic form, a Metal Oxide Semiconductor (MOS) transistor has a gate electrode to which a voltage is applied. The gate is created on the surface of a silicon substrate; the voltage that is applied to the gate creates an electric field that is perpendicular to the interface between the gate electrode and the substrate. The areas in the substrate immediately adjacent to the gate electrode are doped thereby varying their electric conductivity. The areas become the source/drain regions. By varying the voltage that is applied to the gate electrode, the electric field in the gate to substrate interface can be varied and, with that, the current that flows between the source and the drain regions. The electric field therefore controls the flow of current through the device; the device is therefore referred to as the Field Effect Transistor.
The type of device that is created and the type of areas that are created in conjunction with the device are to a large extent determined by the type of dopant that is used and the processing conditions under which the dopants are applied. The creation of semiconductor devices starts with a substrate, which is any material that can retain dopant ions, and the isolated conductivity regions brought about by those ions. Typically, a substrate is a silicon-based material, which receives p-type or n-type ions. The device feature that is being created dictates the type of doping and doping conditions. For instance boron or phosphorous can be used as a dopant and can be doped into polysilicon layers or within polycide gate electrodes.
Channel stop dopants can be p-type or n-type; implants can contain a p-type dopant such as boron implanted at a dose of 5×10
13
atoms/cm
2
at an energy of 35 keV. An n-type dopant is P
31
at a dose in the order of 2.8×10
12
atoms/cm
2
at energy of 60 keV.
A typical conductivity imparting dopant, used to create a lightly doped source and drain region, is phosphorous, ion implanted at an energy between about 5 to 100 KeV, at a dose between about 1E11 to 1E14 atoms/cm
2
. A medium doped source and drain region can be created by using arsenic or phosphorous, ion implanted at an energy between about 5 to 50 KeV, at a dose between about 1E12 to 5E14 atoms/cm
2
. A heavily doped source and drain region can be created by using arsenic, ion implanted at an energy between about 5 to 150 KeV, at a dose between about 1E15 to 1E16 atoms/cm
2
.
Dual gate transistor design is the design where both NMOS and PMOS devices are created on the same chip. Earlier designs of Metal Oxide Semiconductor (MOS) devices primarily used PMOS design because only with p-channel devices using n
+
-doped polysilicon gates and uniform lightly doped n-substrates could acceptable values for V
t
be attained. In its early history, the CMOS transistor was considered to be only an extension of the design for MOS IC's. Later advancements in fabrication technology, mostly due to improvements in ion implant techniques, allowed for the PMOS devices to be replaced with NMOS devices. The larger drive current of NMOS devices resulting in faster speed of these devices resulted in NMOS devices becoming the dominant device type in the IC industry. NMOS devices however exhibited severe limitations in power density and power dissipation causing CMOS devices to become the dominant technology for IC device manufacturing. With the arrival of CMOS devices, a renewed interest in PMOS device developed. CMOS employs both NMOS and PMOS devices to form logic elements. The advantage of CMOS is that its logic devices draw significant current only during the transition from one logic state to the other while drawing very little current between this transition.
The scaling of the CMOS devices in the sub-micrometer device range presents a major challenge. For the fabrication of p-channel and n-channel devices, n
+
doped polysilicon gates are used resulting in functional asymmetry. A number of techniques have been used to assure that the p-channel and n-channel devices are completely symmetrical in their performance characteristics such as threshold voltages, device dimensions and doping while the p-channel device is, for ease of manufacturing, a surface channel device. These devices are made using undoped polysilicon for the gate structures that are simultaneously doped at the time that the source/drain regions of each type of device are implanted. This leads to special manufacturing problems caused by, among others, diffusion of impurity implants through the gate oxide into the channel region thereby changing the threshold voltage of the device. Another concern in creating dual-gate CMOS devices is that various dopants may interdiffuse between adjacent regions, an effect that can become critical at high anneal and other processing temperatures.
Increased CMOS device speed however requires short channel length, the design of p-channel devices with short channel length presents unique problems mostly centered on methods of doping and pocket implants for the device and the impact that these methods have on PMOS device characteristics. A technique used for instance to create deeper and narrower implant is to increase implant energy and implant dosage. This approach however may negate the self-alignment aspect of the implants where the gate electrode serves as a shield and the implants become in this way aligned around the gate electrode. The high implant energy and dosage may result in implant penetration through the gate electrode thereby affecting the gate threshold voltage performance while the high implant may affect the thin layer of gate oxide underlying the gate electrode. It is therefore critical to design an implant method and sequence where gate penetration by implant dopants is not a factor.
Various types of implants are used in the industry to create semiconductor devices. Implants can be a well implant that provides a more uniform background doping. A punch-through implant provides a channel with greater robustness to punch-through voltage. A thresh-hold implant sets the thresh-hold voltage of a device (like an IGFET). The well implant can be provided by boron at a dose in the range of 1×10
12
to 1×10
13
atoms/cm
2
and an energy in the range of 100 to 170 kilo-electron volts, a punch-through implant can be provided by boron at an dose in th
Chen Shui-Hung
Lee Jian-Hsing
Shih Jiaw-Ren
Tunga Chia-Hung
Ackerman Stephen B.
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
Vu David
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