Method of fabricating an ESD protection device

Details Method of fabricating an ESD protection device Method of fabricating an ESD protection device

1999-02-18

2001-07-10

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S277000, C438S278000

Reexamination Certificate

active

06258672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the protection of integrated circuits on a semiconductor substrate from voltage overstress due to pulses resulting from electrostatic discharge (ESD). More particularly, this invention is related to semiconductor devices and structures for improved protection of the integrated circuits.
2. Description of the Related Art
In
FIG. 1
a
the N-channel metal oxide semiconductor (NMOS) field effect transistor (FET)
100
of the prior art is shown in an application, wherein it is configured as an ESD protection circuit. The drain of the NMOS FET
100
is connected to the input pad
115
, the drain of the P-channel Metal Oxide Semiconductor (PMOS) FET
200
, and to the internal circuits
110
. The source and the gate of the PMOS FET
200
are connected to the voltage supply VDD. The source and gate of the NMOS FET
100
are connected to the substrate biasing voltage source Vss. The collectors of the parasitic bipolar junction transistors (BJT's)
140
a
,
140
b
,
140
c
,
140
d
are structurally the drain of the NMOS FET
100
. The emitters of the parasitic BJT's
140
a
,
140
b
,
140
c
,
140
d
are structurally the source of the NMOS FET
100
which is connected to the substrate biasing voltage source Vss. The bases of the parasitic BJT's
140
a
,
140
b
,
140
c
,
140
d
are structurally the channel region of the NMOS FET
100
are connected to the parasitic resistors
145
a
,
145
b
,
145
c
,
145
d
that is formed by the bulk resistance of the semiconductor substrate. The parasitic resistors
145
a
,
145
b
,
145
c
,
145
d
, and
150
a
,
150
b
,
150
c
,
150
d
form a resistive network connected to the ground reference.
A positive ESD source
120
such as the human body or electrostatically charged machinery is momentarily coupled to the input/output pad
115
. The magnitude of a voltage pulse of the ESD source
120
is on the order of 1,000 volts or larger. As the voltage of the ESD source
120
is transferred through the metal connections to the drain of the NMOS FET
100
, the gate to drain voltage of the NMOS FET
100
is exceeds the breakdown voltage. The drain to the substrate junction starts to enter the avalanche breakdown condition and then starts to generate large amounts of electron - hole pairs. The holes pass through the substrate bulk resistances
145
a
,
145
b
,
145
c
,
145
d
, and
150
a
,
150
b
,
150
c
,
150
d
. The voltage drop across the substrate bulk resistances
145
a
,
145
b
,
145
c
,
145
d
, and
150
a
,
150
b
,
150
c
,
150
d
forward bias the source to substrate junction, causing it to emit electrons. This condition starts the parasitic BJT's
140
a
,
140
b
,
140
c
,
140
d
conducting. The substrate bulk resistances,
145
a
,
145
b
,
145
c
,
145
d
, and
150
a
,
150
b
,
150
c
,
150
d
are configured such that the base current of parasitic BJT's
140
a
and
140
b
are much larger than the base current of BJT's
140
c
and
140
d
. Since the base currents are directly related to the collector currents until the parasitic BJT's reach saturation, the currents of the parasitic BJT's
140
a
and
140
b
are much greater than the collector currents of the parasitic
140
c
and
140
d
. This differential of the collector currents commonly called current crowding can cause BJT's
140
a
and
140
b
to fail due to excessive current.
FIGS. 1
b
and
1
c
illustrate the top surface and cross-section of the NMOS FET
100
of
FIG. 11
a
. A P-type material is implanted to a low concentration into the surface of the semiconductor substrate
200
to form the P-well
205
. The P-well
205
forms an expitaxial area that is connected to the substrate biasing voltage source Vss. An N-type material is implanted to a high concentration to form the drain regions
210
a
,
210
b
,
210
c
,
210
d
of the NMOS FET
100
. The N-type material is simultaneously implanted to a high concentration to form the source regions
215
a
,
215
b
,
215
c
of the NMOS FET
100
.
The N-type material is further implanted to a very high concentration within the drain regions
210
a
,
210
b
,
210
c
,
210
d
and the source regions
215
a
,
215
b
,
215
c
, to form respectively low resistivity drain contact points
220
a
,
220
b
,
220
c
,
220
d
and low resistivity source contact points
225
a
,
225
b
,
225
c.
An insulating material is deposited on the surface of the semiconductor substrate
200
in the channel regions
260
a
,
260
b
,
260
c
,
260
d
,
260
e
,
260
f
to form a gate oxide
265
a
,
265
b
,
265
c
,
265
d
,
265
e
,
265
f
. Above the gate oxide
265
a
,
265
b
,
265
c
,
265
d
,
265
e
,
265
f
a conductive material such as highly doped polycrystalline silicon is deposited to form the gates
230
a
,
230
b
,
230
c
,
230
d
,
230
e
,
230
f
of the NMOS FET
100
.
A second conductive material such as a aluminum is then deposited on the surface of the semiconductor substrate
200
to form the connecting lands
240
that connect the drain regions
210
a
,
210
b
,
210
c
,
210
d
to the input/output pad and the internal circuits through the low resistivity drain contacts
220
a
,
220
b
,
220
c
,
220
d
. Simultaneously, the second conductive material is also deposited on the surface of the semiconductor substrate
200
to form the connecting lands
245
from the source regions
215
a
,
215
b
,
215
c
to the substrate biasing source Vss through the low resistivity source contacts
225
a
,
225
b
,
225
c.
The first conductive material is further deposited to form the connecting land
250
that connects the gates
230
a
,
230
b
,
230
c
,
230
d
,
230
e
,
230
f
to the substrate biasing voltage source Vss.
As above described, when an ESD voltage source
120
of
FIG. 1
a
is coupled to the input/output pad
115
, the current crowding that results from nonuniform currents can cause the damage
270
shown.
U.S. Pat. No. 5,237,395 (Lee) describes an electrostatic discharge (ESD) protection circuit for protecting internal devices of an integrated circuit. The ESD protection circuit of Lee is coupled between the power rails of the integrated circuits. First and second current shunt paths between the power rails are maintained nonconductive during normal circuit operation. The ESD protection circuit of Lee causes the first and second current shunt paths to be triggered to a conductive mode in response to an ESD event on the power rails. A triggering circuit to trigger the first and second shunt paths employs a logic gate such as an inverter. The input of the inverter is coupled to the positive power rails and will maintain a low level output during normal operation. The inverter provides a high output in response to an ESD event on the power rail to trigger the first and second shunt paths.
U.S. Pat. No. 5,532,178 (Liaw et al.) teaches an improved process and integrated circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate with an NMOS electrostatic discharge circuit. The NMOS ESD circuit is formed in a P well on the substrate. The improvement includes an ESD NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electrostatic discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.
U.S. Pat. No. 5,689,133 (Li et al.) describes an ESD protection circuit combines a split bipolar transistor with a transistor layout, which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed. The split bipolar transistor structures each combine a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snapback effect to increase current carrying

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