Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-03-30
2001-05-01
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06226211
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a merged memory-logic semiconductor device in which a memory and a logic circuit are implemented on a single semiconductor device.
2. Description of the Related Art
Referring to
FIGS. 1A and 1B
, a conventional merged memory-logic semiconductor device
101
includes a memory
111
, a logic circuit
121
and a built-in self test (BIST) circuit
131
. The memory
111
includes a plurality of memory cells (not shown). The BIST circuit
131
is used to test whether the plurality of memory cells operate normally. The logic circuit
121
stores data in the memory
111
or reads data stored in the memory
111
to perform a certain function. The memory
111
is electrically connected to the logic circuit
121
and the BIST circuit
131
via respective data buses
141
and
143
. The memories
111
shown in FIGS. IA and IB have the same memory capacity, for example,
4
megabits.
Referring to
FIG. 1A
, each of the data buses
141
and
143
are four bits wide. In other words, 4 bits of data are input in parallel into the memory
111
from the logic circuit
121
or the BIST circuit
131
, and, also, four bits of data are output in parallel from the memory
111
to the logic circuit
121
or the BIST circuit
131
. Referring to
FIG. 1B
, data buses
151
and
153
are each eight bits wide. In other words, eight bits of data are input in parallel into the memory
111
from the logic circuit
121
or the BIST circuit
131
, and, also, eight bits of data are output in parallel from the memory
111
to the logic circuit
121
or the BIST circuit
131
. The sizes of the data buses
151
and
153
are determined based on user requirements.
As described above, in the conventional merged memory-logic semiconductor devices
101
, the sizes of the data buses
141
,
143
,
151
and
153
connecting the respective memories
111
to the respective logic circuits
121
and to the respective BIST circuits
131
, are determined based on user requirements, although the memories
111
have the same capacity. For this reason, not only is it expensive to develop the merged memory-logic semiconductor device
101
, but it also takes longer for the BIST circuit
131
to test the memory
111
as the width of the data buses
141
,
143
,
151
and
153
becomes smaller.
SUMMARY OF THE INVENTION
According to the present invention, a merged memory-logic semiconductor device is provided in which, for a given memory capacity, the same design of a single built-in self test (BIST) circuit is used regardless of the size of a data bus connecting the memory to a logic circuit.
According to one aspect of the present invention a merged memory-logic semiconductor device is provided which comprises: a memory having a first data bus of a first bus width for parallel data input and output to the memory; a control unit connected to the first data bus; a logic circuit connected to the control unit by a second data bus having a width less than the width of the first data bus, the logic unit being operative to write data to the memory and read data from the memory; and a built-in self test circuit for testing the memory, the built-in self test unit being connected to the control unit by a third data bus, the control unit being operative to connect the logic circuit to the memory in a read/write mode and being operative to connect the built-in self test circuit to the memory in a test mode. According to another aspect of the present invention, in the merged memory-logic semiconductor device of the foregoing aspect, the width of the third data bus is equal to the width of the first data bus. In yet another aspect, in the merged memory-logic semiconductor device of the first aspect the control unit comprises: a control signal generator for generating a read/write control signal and a test control signal in response to receipt of a signal; and a read/write control driver connected to the control signal generator to receive a read/write control signal and a test control signal, said read/write control driver being operative responsive to receipt of a read/write control signal to connect the logic circuit to the memory, and being operative in response to receipt of a test control signal to connect the built-in self test circuit to the memory.
In accordance with a further aspect of the present invention, a method of manufacturing a merged memory-logic semiconductor device is provided in which the method comprises: providing a memory having a first data bus of a first bus width for parallel data input and output to the memory; providing a control unit and connecting the control unit to the first data bus; providing a logic circuit and connecting the logic circuit to the control unit by a second data bus having a width less than the width of the first data bus; and providing a built-in self test circuit for testing the memory, and connecting the built-in self test circuit to the control unit by a third data bus.
According to the present invention, the testing time for a memory provided in a merged memory-logic semiconductor device is shortened.
REFERENCES:
patent: 5848016 (1998-12-01), Kwak
patent: 5926420 (1999-07-01), Kim
patent: 6108252 (2000-08-01), Park
patent: 6158036 (2000-12-01), Kwak
Heid David W.
Phan Trong
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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