Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-03-01
2001-04-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000
Reexamination Certificate
active
06221793
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and in particular, to the formation of a very thin oxide layer on a semiconductor wafer.
BACKGROUND OF THE INVENTION
Various integrated circuits utilize structures formed with a thin layer of silicon dioxide (SiO
2
) for various purposes. For example, a thin layer of silicon dioxide is used as a protection structure for on-chip resistors. As integrated circuit technologies become smaller, it is advantageous for all structures to become smaller, including thin silicon dioxide layers.
Suitably thin silicon dioxide layers can be formed using a conventional method of thermal oxide deposition. However, the high thermal budget associated with thermal oxide consumes silicon and drives source/drain (S/D) implantation further so that the source/drain implant is not easily controlled.
An advantageous alternative to thermal oxide deposition of thin silicon dioxide layers is deposition using the plasma-enhanced chemical vapor deposition (PECVD) technique. However, one of the concerns with conventional PECVD methods is that they do not allow deposition of layers less than about 1000 angstroms.
The process for producing a very thin (less than 350 angstroms) layer of silicon dioxide by PECVD was described in U.S. Pat. No. 5,736,423. In this reference, the time duration of pre-coating and soak time steps of the PECVD process were substantially increased, and the flow of silane (SiH
4
) was substantially reduced, as well as the applied pressure and high-frequency power. Deposition rates were lowered from the previously conventional process of 5500 angstroms per minute to 1700 angstroms per minute.
Although U.S. Pat. No. 5,736,423 provides a process that reduces the deposition rate to provide a more controllable process, further improvements in the deposition rate for a better process control are desirable. At the same time, with a super low deposition rate, the film still needs to be dense, silicon rich, highly compressive, with excellent step coverage and acceptable thickness uniformity.
SUMMARY OF THE INVENTION
There is a need for a method of providing a super low deposition rate, very thin deposition layer of PECVD oxide, with excellent step coverage.
These and other needs are met by embodiments of the present invention which provide a method of depositing oxide on a wafer in a PECVD reactor. The method includes the steps of applying reactant gases to the wafer, including: silane (SiH
4
) at a flow rate in a range from 10 to 60 sccm; nitrous oxide (N
2
O) at a flow rate in a range from 200 to 1000 sccm; and nitrogen (N
2
) at a flow rate in a range from 4000 to 8000 sccm. Reactor pressure is maintained between 3 to 7 torr, and RF power is applied between 100 and 170 watts.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of forming a semiconductor device arrangement comprising forming a gate having sidewalls and depositing on the gate sidewalls by PECVD a layer of oxide less than 200 angstroms thick at a deposition rate less than 20 angstroms per second. Nitride spacers are then formed on the oxide layer. Forming the undoped oxide liner with a super low deposition rate as provided in the present invention, when used together with the nitride spacer, may improve P channel Idsat:Idoff by a significant amount when compared to that of LPCVD (low pressure chemical vapor deposition) processes.
The earlier stated needs are also met by another embodiment of the present invention that provides a semiconductor device arrangement comprising a gate having sidewalls, an oxide liner on the gate sidewalls, and nitride spacers on the oxide liner. The oxide liner is a super low deposition rate PECVD oxide layer having a deposited thickness of less than 200 angstroms. In certain embodiments, the super low deposition rate PECVD oxide layer has a refractive index greater than or equal to 1.48, a thickness non-uniformity of 1.1% or less, and step coverage of 90% or greater.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5736423 (1998-04-01), Ngo
patent: 5904529 (1999-05-01), Gardner et al.
patent: 6077764 (2000-06-01), Sugiarto et al.
Huertas Robert A.
Ngo Minh Van
Ruelke Hartmut
Advanced Micro Devices , Inc.
Ghyka Alexander G.
Niebling John F.
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