Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-24
2001-09-18
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S783000
Reexamination Certificate
active
06291295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a storage node of a capacitor.
2. Description of the Related Art
As the integration of semiconductor devices increases, sizes of semiconductor devices must be decreases in accord with a design rule. However, as the size of a DRAM (dynamic random access memory) decreases, the capacitance of a DRAM capacitor is correspondingly reduced. Therefore, it is necessary to refresh the capacitor frequently. In order to decrease the refreshing frequency, the capacitance of the capacitor must be increased. Methods for increasing the storage capacitance of the capacitor include (1) increasing the surface area of a capacitor; (2) selecting a dielectric material with a high dielectric constant; and (3) reducing the thickness of a dielectric layer. Because of the limitation in dielectric materials and fabrication techniques, only limited reduction can be made in the thickness of the dielectric layer.
An electrode with a hemispherical grained silicon (HSG-Si) layer with increased surface area is commonly used in a storage electrode for increasing the capacitance of a capacitor. Since the HSG-Si layer is formed at a high temperature, an out-gassing problem easily occurs in an inter-poly dielectric (IPD) layer. The gas generated from the IPD layer easily is easily adsorbed to the surface of the storage electrode and retards the silicon migration of the storage electrode. Thus, the formation of the HSG-Si layer the storage electrode is suppressed. The conventional method solves the out-gassing problem by forming a silicon nitride layer on the IPD layer. However, this causes a poor etching selectivity during the formation of the hemispherical grains. That is, silicon atoms also migrate on a surface of the silicon nitride layer to affect the insulation performance of the IPD layer.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a storage electrode. An isolation layer is formed on a substrate. An ion implantation step is performed. The to isolation layer is patterned to form an opening. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is formed on the conductive layer. In the invention, the sequence of the ion implantation step can be changed as specifically required. The ion implantation can also be performed after the opening is formed.
The material of the isolation layer comprises borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), plasma-enhanced tetra-ethyl-ortho-silicate (PE TEOS), and TEOS-based oxide. The isolation layer may further comprise a sandwich structure comprising a silicon nitride layer or a silicon-oxy-nitride layer as an inner layer. The silicon nitride layer or a silicon-oxy-nitride layer is formed to suppress out-gassing.
The ion implantation is performed to prevent C—H bonds and C—O bonds in the isolation layer from breaking during a subsequent thermal step. The ion implantation step is used for preventing the isolation layer from generating gas. Thus, the present invention increases the formation of the HSG-Si layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5656860 (1997-08-01), Lee
patent: 5721153 (1998-02-01), Kim et al.
patent: 5723373 (1998-03-01), Chang et al.
patent: 5923989 (1999-07-01), Lin et al.
Huang Kuo-Tai
Lur Water
Yew Tri-Rung
Chaudhuri Olik
Pham Hoai
United Microelectronics Corp.
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