Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-15
2001-05-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S291000, C438S231000
Reexamination Certificate
active
06232160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of replacing an anti-punch through implant and a pocket implant with a single delta-channel implant in the fabrication of integrated circuits.
2. Description of the Prior Art
In scaling down semiconductor devices to the deep sub-micron regime, higher doped channels are required for short channel devices. Normally, an anti-punch through implant and a large angle pocket implant are made into the channel region before gate oxidation. The anti-punch through implant inhibits source/drain leakage and the pocket implant suppresses drain induced barrier lowering (DIBL) of the anti-punch through implant. However, the increased channel doping will also increase junction capacitance, junction leakage, and reverse short-channel effect. It is desired to suppress short-channel effect without increasing junction capacitance and leakage.
A number of U.S. Patents teach various methods of LDD and anti-punch through implants. U.S. Pat. No. 5,766,998 to Tseng discloses a polysilicon masking layer with spacers and two ion implants—for punch through and threshold voltage adjustment. U.S. Pat. No. 5,538,913 to Hong teaches an anti-punch through implant masked by conducting spacers which become part of the gate. U.S. Pat. No. 5,434,093 to Chau teaches an anti-punch through implant using oxide spacers as a mask. The oxide spacers remain. U.S. Pat. No. 5,698,461 to Liu also teaches an anti-punch through implant. U.S. Pat. No. 5,429,956 to Shell et al teaches an anti-punch through implant through polysilicon narrowed by oxide spacers. U.S. Pat. No. 5, 677,218 to Tseng shows an ion implant through a mask and polysilicon layer.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of suppressing short channel effect without increasing junction leakage and capacitance.
Yet another object is to provide a method of self-aligning anti-punch through implant without an additional mask.
A further object of the invention is to provide a method of replacing an anti-punch through implant and a pocket implant with a single delta-channel implant.
A still further object is to provide a method of suppressing short-channel effect without increasing junction leakage and capacitance using a single delta-channel implant.
Yet another object is to provide a method of suppressing short-channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant.
In accordance with the objects of this invention, a method of suppressing short-channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is achieved. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short-channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening. The silicon nitride layer is removed to form a gate electrode wherein the delta-channel implant underlies the gate electrode. Thereafter, lightly doped regions and source and drain regions are formed within the semiconductor substrate associated with the gate electrode to complete fabrication of the integrated circuit device.
REFERENCES:
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5538913 (1996-07-01), Hong
patent: 5677218 (1997-10-01), Tseng
patent: 5686321 (1997-11-01), Ko et al.
patent: 5698461 (1997-12-01), Liu
patent: 5712501 (1998-01-01), Davies et al.
patent: 5712503 (1998-01-01), Kim et al.
patent: 5766998 (1998-06-01), Tseng
Chen Shui-Hung
Lee Jian-Hsing
Shih Jiaw-Ren
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Pike Rosemary L. S.
Saile George O.
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