Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-09-08
2001-01-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S783000
Reexamination Certificate
active
06175162
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit (IC) devices and, more particularly, to a semiconductor wafer having a bottom surface that is coated with a protective coating prior to the performance of a wafer dicing, or die singulation, operation.
Currently, in order to remain competitive in the IC industry, IC process engineers must continuously increase device yield per wafer or lot. That is, process engineers seek to increase the number of usable semiconductor devices per wafer. Since any step in the fabrication process may detrimentally affect the IC device yield, process engineers seek to optimize each step and, as a result, reduce the number of lost IC devices for the optimized step.
For example, a conventional dicing, or sawing, process is one fabrication step that is likely to result in a substantial loss of devices. In general, when a wafer is diced, chipping may occur along the dicing edges of the individual IC devices. This chipping may then lead to the formation of cracks throughout the IC device, which cracking may damage the IC device and make the IC device unusable for its intended application. In other words, the chipping results in IC devices that are more vulnerable to stress and more susceptible to damage. As a result of an increase in unusable IC devices due to chipping, the IC device yield per wafer or lot is significantly reduced, and product reliability is compromised.
One type of IC device that may be chipped during the dicing operation is a flip chip device. During the dicing process, the flip chip device is cut away from the other flip chip devices of the wafer. The separated flip chip device may have, for example, rough edges as a result of the dicing process. After the flip chip device is separated from the other flip chip devices, the flip chip device is then packaged and/or mounted to a printed circuit board. As a result of chipping, the flip chip device may suffer various form of damage at any point subsequent to the dicing process. For example, the flip chip device may be damaged while it is being handled prior to mounting or packaging.
FIG. 1
is a side view of a conventional flip chip type device
100
. The flip chip
100
includes a die
102
that typically has a plurality of conventionally fabricated IC device structures. These IC device structures may include, for example, transistors and interconnect layers. The die
102
has a top surface
108
that includes bump pads (not shown). Bumps
106
are formed on the bump pads of the top most surface
108
. This top surface
108
is opposite a bottom surface
104
of the die
102
. The bottom surface
104
is conventionally left bare, or exposed For example, the bottom surface
104
is bare silicon.
There are many problems associated with a conventional wafer that has conventional devices with exposed bottom surfaces. For example, one problem is the aforementioned chipping during the dicing operation. That is, the exposed bottom surface fails to provide sufficient mechanical protection under certain stress inducing conditions. The exposed bottom surface also fails to provide protection from electrostatic shock or light induced bias for flip chip applications. That is, the devices may have functional problems due to photogenerated carriers when the bottom surface (e.g.,
104
) of the die (e.g,
102
) is exposed to light, or the devices may be subject to an undesirable electrostatic shock during handling of the device subsequent to the dicing operation.
The aforementioned problems all contribute to a decrease in production yield. Consequently, there is a need for an improved wafer that provides a solution to the aforementioned problems. For example, there is a need for an improved wafer that is less susceptible to mechanical stress during and after a dicing operation. Additionally, there is a need for a method for making such an improved wafer.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and according to the purpose of the present invention, a packaged integrated circuit device is disclosed. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils.
In another embodiment, a semiconductor wafer is disclosed. The wafer includes a multiplicity of semiconductor dies, and each die has a plurality of electrical contacts that are exposed on a first surface of the wafer. The wafer further includes a protective thick film adhered directly to a second surface of the wafer. The protective film is thick enough to allow laser marking of the protective film without the laser penetrating to the die.
In another aspect of the invention, a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies is disclosed. The method includes providing a plurality of dies on the top surface of the wafer substrate. A plurality of electrical contacts are disposed on each die. The method further includes printing a thick film upon the bottom surface of the wafer substrate such that the thick film is thick enough to allow laser marking of the thick film without the laser penetrating to one of the plurality of dies. In a preferred embodiment, the printing act includes placing a screen across the bottom surface of the wafer substrate, where the screen has a first end and a second end that is opposite the first end, depositing a predefined amount of material at the first end of the screen, and dragging a squeegee from the first end to the second end of the screen such that the material is thinly deposited through the screen and across the bottom surface of the wafer substrate to form the thick film. In another preferred embodiment, the method further includes adhering a mounting tape to the thick film, and dicing the wafer such that the dies are separated from each other. The mounting tape is not an especially adhesive type tape.
In another embodiment, a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies is disclosed. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is a UV type tape, and dicing the wafer to separate the dies. In this embodiment, the thick film reduces chipping along edges of the separated dies.
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patent: 5504374 (1996-04-01), Oliver et al.
patent: 5536970 (1996-07-01), Higashi et al.
patent: 5892288 (1999-04-01), Muraki et al.
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patent: 6034437 (2000-03-01), Shibata
patent: 61-84824 (1986-04-01), None
patent: 63-285955 (1988-11-01), None
patent: 4-116955 (1992-04-01), None
Kao Pai-Hsiang
Kelkar Nikhil Vishwanath
Schaefer William Jeffrey
Beyer Weaver & Thomas LLP
Clark Sheila V.
National Semiconductor Corporation
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