Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-10-20
2001-01-16
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S003000, C438S240000, C438S250000, C438S393000
Reexamination Certificate
active
06174822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The entire disclosure of U.S. patent application Ser. No. 09/103,873 filed Jun. 24, 1998 is expressly incorporated by reference herein.
The present invention relates to a semiconductor device including a capacitor having a dielectric film formed of a dielectric material having a high dielectric constant or a ferroelectric material, and a method for fabricating the same.
2. Description of the Related Art
Recently, as functions of consumer electric and electronic appliances have been more and more advanced along with higher processing rates and lower power consumption of microcomputers, the size of semiconductor devices used in the microcomputers has rapidly decreased. This has been accompanied by the serious problem of unnecessary radiation, which is electromagnetic wave noise generated from the electric and electronic appliances.
In order to reduce the unnecessary radiation, technologies for incorporating a capacitor having a large capacitance including a dielectric film formed of a dielectric material having a high dielectric constant (hereinafter, referred to as a “high dielectric constant material film”) into a semiconductor device have been the target of attention. Furthermore, in accompaniment of higher integration dynamic RAMs (DRAMs), technologies for using a high dielectric constant material film in the capacitor, in lieu of a silicon oxide film and a silicon nitride film which are conventionally used, have been widely studied.
Furthermore, in order to realize non-volatile RAMs which are operable at lower voltages and provide higher read/write rates, ferroelectric material films exhibiting spontaneous polarization have been actively studied.
The most important point in realizing semiconductor devices having the above-described features is to develop a structure which permits multi-layered interconnects without deteriorating the characteristics of the capacitor and a method for fabricating such a structure.
Hereinafter, an exemplary conventional method for fabricating a semiconductor device
500
will be described with reference to
FIGS. 10A through 10E
(cross-sectional views).
As shown in
FIG. 10A
, an integrated circuit
4
and a device isolating insulating layer
5
are formed on a supporting substrate
1
. The integrated circuit
4
includes a MOS field effect transistor (MOSFET) having a gate electrode
2
, and source and drain regions
3
. An insulating layer
6
is formed on the resultant laminate. A film which will act as a lower electrode
7
of a capacitor
10
is formed on the insulating layer
6
by sputtering or electron beam deposition. Then, a dielectric film
8
made of a high dielectric constant material film or a ferroelectric material film is formed on the film to act as the lower electrode
7
by metal organic deposition, metal organic chemical vapor deposition, or sputtering. Subsequently, a film which will act as an upper electrode
9
is formed on the dielectric film
8
by sputtering or electron beam deposition. Then, the layers
7
,
8
and
9
are patterned into desirable patterns, thereby forming a capacitor
10
.
Next, as shown in
FIG. 10B
, a first interlayer insulating film
11
is formed on the insulating layer
6
so as to cover the capacitor
10
. Contact holes
12
are formed so as to run through the first interlayer insulating film
11
and reach, respectively, the lower electrode
7
and the upper electrode
9
of the capacitor
10
. Contact holes
13
are also formed so as to run through the first interlayer insulating film
11
and the insulating layer
6
and reach, respectively, the source and drain regions
3
. Conductive layers are formed on the first interlayer insulating film
11
and in the contact holes
12
and
13
by sputtering or the like, and patterned into desired patterns. Thus, first interconnects
14
for electrically connecting the integrated circuit
4
and the capacitor
10
are formed. The first interconnects
14
are then subjected to a thermal treatment.
As shown in
FIG. 10C
, a second interlayer insulating film
15
are formed on the resultant laminate so as to cover the first interconnects
14
. The second interlayer insulating film
15
is formed by substantially planarizing, by etch-back, a silicon oxide film formed by plasma CVD using tetraethyl orthosilicate (TEOS) (hereinafter, referred to as a “plasma TEOS film”) or a laminate including the above-described plasma TEOS film and a silicon-on-glass (SOG) film.
As shown in
FIG. 10D
, contact holes
16
are formed so as to run through the second interlayer insulating film
15
and reach the first interconnects
14
. Second interconnects
17
are selectively formed on the second interlayer insulating film
15
and in the contact holes
16
so as to be electrically connected to the first interconnects
14
. The second interconnects
17
are then subjected to a thermal treatment.
As shown in
FIG. 10E
, a passivation layer
18
is formed so as to cover the second interconnects
17
on the resultant laminate. Thus, the semiconductor device
500
is fabricated.
In the above-described method for fabricating the semiconductor device
500
, the second interlayer insulating film
15
needs to be formed so as to have no step and a flat top surface and thus have a sufficient step coverage property. The reason for this is that, when the second interlayer insulating film
15
has a step, the second interconnects
17
to be formed thereon may disadvantageously be disconnected at the step. Accordingly, the conventional second interlayer insulating film
15
formed of a plasma TEOS film or the like needs to have a thickness h
1
(
FIG. 10C
) of about 1 &mgr;m or more on the first interconnects
14
above the upper electrode
9
and also have a thickness h
2
(
FIG. 10C
) of about 2 &mgr;m or more on the first interlayer insulating film
11
on an edge of the dielectric film
8
formed of a high dielectric constant material film or a ferroelectric material film.
Generally, however, when the force per unit thickness is constant, a thicker layer results in a stronger tensile or compressive stress. Thus, when the thickness of the second interlayer insulating film
15
is as thick as above-described, a significantly strong stress is applied to the capacitor
10
provided below the second interlayer insulating film
15
.
Specifically when the second interlayer insulating film
15
is formed of a plasma TEOS film, the compressive stress acting on the dielectric film
8
prevents the polarization of the dielectric material forming the dielectric film
8
. As a result, the physical properties of the dielectric film
8
formed of the high dielectric constant material or ferroelectric material deteriorate.
As used herein, the term “stress” refers to a force for contracting the layer (hereinafter, referred to as a “tensile stress”) and/or a force for expanding the layer (hereinafter, referred to as a “compressive stress”).
SUMMARY OF THE INVENTION
A semiconductor device of the present invention includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
In one embodiment, the dielectric film is formed from either a dielectric material having a high dielectric constant or a ferroelectric material.
In one embodiment, the second in
Fujii Eiji
Judai Yuji
Kutsunai Toshie
Nagano Yoshihisa
Uemoto Yasuhiro
Jr. Carl Whitehead
Matsushita Electronics Corporation
Ratner & Prestia
Vockrodt Jeff
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