Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1999-06-17
2001-08-28
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S791000, C438S769000, C438S597000, C438S533000
Reexamination Certificate
active
06281143
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor manufacturing in general, and more specifically to methods for forming borderless contact.
2. Description of the Prior Art
The major objectives of the semiconductor industry have been to continually increase the device and circuit performances of silicon chips, while maintaining or even decreasing the cost of producing these same silicon chips. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate silicon devices, with sub-micron features. The ability to use sub-micron features, or micro-miniaturization, has allowed performance improvements to be realized by the reduction of resistances and parasitic capacitances, resulting from the use of smaller features. In addition, the use of sub-micron features, results in smaller silicon chips with increased circuit densities, thus allowing more silicon chips to be obtained from a starting silicon substrate, thus reducing the cost of an individual silicon chip.
The attainment of micro-miniaturization has been basically a result of advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching. The development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron features in photoresist layers to be routinely achieved. In addition, similar developments in the dry etching discipline have allowed these sub-micron images in photoresist layers to be successfully transferred to underlying materials, which are used for the creation of advanced semiconductor devices. However, the use of sub-micron features can improve silicon device performance and decrease silicon chip cost, but will introduce specific semiconductor fabrication problems that would be encountered by larger featured counterparts. For example, specific designs, which are used to connect an overlying metallization structure to an underlying metallization structure, sometimes require that metal filled via holes in insulator layers, and not always be fully landed. That is the metal filled via, not being placed entirely on the underlying metallization structure. The inability to fully land a via on an underlying metal structure places a burden on the process used to create the via hole. For example if the chip design demands a non-fully landed, or a borderless contact, the dry etching procedure used to create the via has to be able to insure complete removal of insulator material from the area where the via landed on the underlying metal structure. Therefore, the dry etching procedure necessitates the use of an overetch cycle.
However, the overetching can create problems.
FIG. 1A
to
FIG. 1D
are schematic representations of structures at various stages during the formulation of borderless contact using conventional, prior art techniques. A substrate
100
is provided with a source/drain junction
110
formed therein, as shown in
FIG. 1A. A
shallow trench isolation (STI)
120
is formed beside the junction
110
. Then, a silicon nitride layer
140
is deposited on the substrate
100
as a stop layer, as shown in
FIG. 1B. A
planarized interlevel dielectric layer
150
is subsequently formed over the stop layer
140
. The formulation of contact includes two etching steps, i.e., etching interlevel dielectric layer
150
is the first and etching stop layer
140
is the second.
FIG. 1C
shows the first step and
FIG. 1D
shows the second step. While in the second step, the selectivity between silicon nitride and silicon oxide is about 1.5:1. This will make overetching on top surface of STI
120
near bottom of junction
110
, and leakage current will occur between side wall of STI
20
and substrate
100
when a tungsten or a copper plug fills the contact
160
, as shown in FIG.
1
D.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming borderless contact that substantially simplifies the process by reducing one etching blanket silicon nitride step.
It is another object of this invention to minimize the trench isolation loss.
It is a further object of this invention that no silicon nitride stress issue on source/drain to cause device impact.
In one embodiment, a substrate is provided with active areas and a trench isolation region in which the active areas are silicide. Then, the substrate is nitridized so that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. This nitridation is performed by applying NH
3
gas after/with rapid thermal process 2 of salicide process. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.
REFERENCES:
patent: 5474953 (1995-12-01), Shimizu et al.
patent: 5821153 (1998-10-01), Tsai et al.
patent: 5827764 (1998-10-01), Liaw et al.
patent: 5948702 (1999-09-01), Rotundaro
patent: 6066555 (2000-05-01), Nulty et al.
Huang Michael W C
Shih Hsueh-Hao
Yang Gwo-Shii
Yew Tri-Rung
Elms Richard
Pyonin Adam
United Microelectronics Corp.
LandOfFree
Method of forming borderless contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming borderless contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming borderless contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2436582