Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-11
2001-07-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06261911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a junction in a semiconductor device, and more particularly to a method of manufacturing a junction in a semiconductor device capable of improving a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (ESD) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as capable of increasing the electric current density by lowering the series resistance of source/drain extension.
2. Description of the Prior Arts
Generally, as semiconductor devices become high-integrated, small-sized and high-speed, it is required to improve a short channel characteristic, a junction leakage characteristic and a contact resistance characteristic in the buried channel field effect transistor. The buried channel field effect transistor has been found to show the good improvement in its characteristic when an elevated source/drain junction fabricated by a selective epitaxial growth is applied thereto.
FIGS. 1A
to
1
C are cross sectional views of the device illustrating a method of manufacturing a conventional semiconductor device.
With reference to
FIG. 1A
, a device separating film
12
is form on the semiconductor substrate
11
to define an active region, and then a gate oxide film
13
, a gate electrode
14
and a mask insulating film
15
are successively formed.
In
FIG. 1B
, a gate spacer
16
is formed on the side wall of the pattern on which the gate oxide film
13
, gate electrode
14
and mask insulating film
15
have successively been deposited, and then a non-doped epi-silicon layer
17
is selectively formed on only an exposed portion of the semiconductor substrate
11
using a chemical vapor deposition (CVD) process. On a portion adjacent the gate side-wall spacer
16
with respect to the epi-silicon layer
17
fabricated by the selective epitaxial growth technique, there occurs a facet
19
having a relatively large angle of 30 to 60°. Herein, prior to growing the epi-silicon layer
17
, a native oxide film created on the surface of the semiconductor substrate
11
is removed using a wet cleaning process.
FIG. 1C
shows processes for form an elevated source/drain junction. As shown, a source/drain ion implantation process is performed, and then there performed a thermal annealing for activating the ion-implanted dopants. The dopants are diffused into the semiconductor substrate
11
thereby to form a diffusion region
18
. As a result, there formed an elevated source/drain junction
178
consisting of the doped epi-silicon layer
17
and the diffusion region
18
. In the source/drain ion implantation process, a P-type impurity ion is applied since the buried field effect transistor is P-channel.
In the elevated source/drain junction
178
fabricated by such conventional method, as shown in
FIG. 1B
, the epi-silicon layer
17
formed using the selective epitaxial growth technique causes a facet
19
to occur on a portion adjacent the gate side-wall spacer
16
with respect to it. Such facet
19
has been disclosed by C. Mazure et al., “IEDM, p853 (1992)”. As shown in
FIG. 1C
, this facet
19
causes a local increase of the depth of the diffusion region
18
formed within the semiconductor substrate
11
beneath the epi-silicon layer
17
upon the source/drain implant. That is, the profile of the diffusion region
18
formed by the source/drain ion implantation process becomes deep in the portion (
18
A) adjacent the channel, resulting in the increase of the drain induced barrier lowing (DIBL) effect in the elevated source/drain junction
178
. As a result, a short channel characteristic becomes worse to the extent that makes an application of the field effect transistor using the buried channel difficult. Such a relationship between the facet
19
and DIBL effect has been discussed by J. J. Sun et al., “IEEE ED-45 [6], p1377 (1998)”.
In order to solve the problem due to the facet
19
, several improvements have been disclosed by J. J. Sun et al., “IEEE ED-45 [6], p137 (1998)” and C. P. Chao, et at., “IEDM, p103 (1997)”. However, these improvements also cause the complexity in other processes. In addition, in order to remove the cause of the local increase of the depth of the diffusion region
18
, T. Tanaka et al., “Symp. On VLSI Tech., p88 (1998)” apply a new dopant such as decarborane, B
10
H
14
.
In the meantime, K. Miyano et al., “Ext. Abst. Of SSDM, p420 (1998)” disclose that a spacer undercut is induced by a negative slope of the side-wall spacer and thus a silicon is somewhat penetrated into the undercut during the selective epitaxial growth (SPG) process. Also, Jung Ho Lee et al., “J. Kor. Phys. Soc., 33 s302 (1998)” discloses that the facet may be minimized by the aid of the stacking fault (SF).
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method of manufacturing a junction in a semiconductor device capable of improving a short channel characteristic by suppressing a facet occurred when forming the elevated source/drain junction of the buried channel field effect transistor using a selective epitaxial growth technique as well as capable of increasing an electric current density by lowering the series resistance of source/drain extension.
To accomplish the object, the method in accordance with the present invention comprises the steps of:
successively forming a gate oxide film, a gate electrode and a mask insulating film on the semiconductor substrate;
forming a spacer on side wall of the gate electrode in which the spacer has a double-film structure of an oxide film and a nitride film;
performing a cleaning process for forming an undercut on the spacer and removing a native oxide film created on the surface of the semiconductor substrate;
forming an epi-silicon layer on an exposed portion of the semiconductor substrate so that a stacking fault is formed on a portion adjacent the spacer with respect to the epi-silicon layer and a self-aligned epitaxial silicon sliver is formed on the undercut portion;
performing a source/drain ion implantation process; and
performing a thermal annealing for activating the ion-implanted dopants so as to form an elevated source/drain junction.
REFERENCES:
patent: 4728623 (1988-03-01), Lu et al.
patent: 4738937 (1988-04-01), Parsons
patent: 4918029 (1990-04-01), Kim
patent: 5004702 (1991-04-01), Samata et al.
patent: 5030583 (1991-07-01), Beetz, Jr.
patent: 5032538 (1991-07-01), Bozler et al.
patent: 5045494 (1991-09-01), Choi et al.
patent: 5272109 (1993-12-01), Motoda
patent: 5322802 (1994-06-01), Baliga et al.
patent: 5322814 (1994-06-01), Rouse et al.
patent: 5378652 (1995-01-01), Samata et al.
patent: 5432121 (1995-07-01), Chan et al.
patent: 5435856 (1995-07-01), Rouse et al.
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5508225 (1996-04-01), Kadoiwa
patent: 5567652 (1996-10-01), Nishio
patent: 5599724 (1997-02-01), Yoshida
patent: 5627102 (1997-05-01), Shinriki et al.
patent: 5633201 (1997-05-01), Choi
patent: 5744377 (1998-04-01), Sekiguchi et al.
patent: 5773350 (1998-06-01), Herbert et al.
patent: 5804470 (1998-09-01), Wollesen
patent: 5840604 (1998-11-01), Yoo et al.
patent: 5970351 (1999-10-01), Takeuchi
patent: 5998248 (1999-12-01), Ma et al.
patent: 5998273 (1999-12-01), Ma et al.
patent: 6022771 (2000-02-01), Ma et al.
patent: 6025242 (2000-02-01), Ma et al.
patent: 6117741 (2000-09-01), Chatterjee et al.
patent: 6127232 (2000-10-01), Chatterjee et al.
patent: 6156613 (2000-12-01), Wu
patent: 6177323 (2001-01-01), Wu
patent: 6190977 (2001-02-01), Wu
patent: 54-158880 (1979-12-01), None
patent: 2-37745 (1990-02-01), None
patent: 2-260667 (1990-10-01), None
patent: 8-236728 (1996-09-01), None
patent: 10-107219 (1998-04-01), None
patent: 11-97519 (1999-04-01), None
High Performance Buried Channel-pFETs Using Elevated Source/Drain Structure with Self-Aligned Epitaxial Silicon Sliver (SESS), Lee et al., Extended Abstracts of the 1999
Kwak Noh Yeal
Lee Jung Ho
Lee Sahng Kyoo
Lee Seung Chul
Yeo In Seok
Gurley Lynn A.
Hyundai Electronics Industries Co,. Ltd.
Niebling John F.
Pennie & Edmonds LLP
LandOfFree
Method of manufacturing a junction in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a junction in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a junction in a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2435197