Low power data latch with overdriven clock signals

Details Low power data latch with overdriven clock signals Low power data latch with overdriven clock signals

1995-07-05

1996-10-22

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365233, 327199, 327208, 327212, G11C 700, H03K 1756

Patent

active

055684297

ABSTRACT:
A data latch with reduced data signal leakage includes a latch circuit and a clock buffer circuit which provides a differential clock signal to the input transmission gate of the latch circuit. The clock buffer circuit is biased between upper and lower supply voltage potentials which are higher and lower, respectively, than those between which the latch circuit is biased. This causes the differential clock signal to be overdriven with respect to the incoming data signal which is latched by the latch circuit. As a result, the input transmission gate of the latch circuit is reverse-biased during the inactive state of the differential clock signal, thereby isolating the storage node within the latch circuit and preventing signal leakage therefrom.

REFERENCES:
patent: 5250852 (1993-10-01), Ovens et al.
patent: 5260903 (1993-11-01), Suyama et al.

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