Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-10
1999-10-19
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438301, 438231, H01L 21336
Patent
active
059703512
ABSTRACT:
A method of producing a transistor having a source and drain diffusion layer formed so that is has a junction of a shallow depth and is low in parasitic resistance and parasitic capacitance. The method allows the manufacture of a transistor having a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode formed on the gate insulator, and source and drain diffusion layers of one conductivity type formed on the principal plane of the semiconductor substrate across the gate electrode. A semiconductor thin film layer doped with an impurity of the same conductivity type is selectively deposited on the principal plane of the semiconductor substrate on which the source and drain diffusion layers are formed. A facet face is formed at an end portion of the semiconductor thin film which opposes to a sidewall of the gate electrode. The facet face has an inclination angle between a sidewall face of the gate electrode and the principal plane of the semiconductor substrate.
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H. Shibata et al., "High Performance Half-Micron PMOSFETs with 0.1 .mu.m Shallow P.sup.+ N Junction Utilizing Selective Silicon Growth and Rapid Thermal Annealing," 1987 IEEE, IEDM 87, pp. 590-593.
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K. Goto et al., "A Novel Fabrication Method for Short Channel MOSFETs Using Self-Aligned Ultrashallow Junction Formation by Selective Si.sub.1-x Ge.sub.x CVD," Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp. 999-1000.
Murphy John
NEC Corporation
Niebling John F.
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