Method of forming asymmetrically doped source/drain regions

Details Method of forming asymmetrically doped source/drain regions Method of forming asymmetrically doped source/drain regions

1998-11-20

2000-10-31

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, H01L 21336

Patent

active

061401862

ABSTRACT:
Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

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Horiuchi et al., "An Asymmetric Sidewall Process for High Performance LDD MOSFET's", IEEE Transactions on Electron Devices, vol. 41, No. 2, Feb. 1994, pp. 186-190.

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