Method of forming a non-volatile memory array

Details Method of forming a non-volatile memory array Method of forming a non-volatile memory array

1995-05-19

1997-08-26

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438586, 438588, H01L 218247

Patent

active

056610548

ABSTRACT:
A method of forming a non-volatile memory array includes, a) providing first and second floating gate word lines atop a semiconductor substrate, the first and second word lines being adjacent one another and defining transistor active area therebetween, the first and second word lines having inwardly opposing and facing active area sidewall edges, the first and second word lines each comprising respective nitride capping layers having a thickness of at least about 1000 Angstroms; b) providing a nitride spacer layer over the nitride capping layer; c) anisotropically etching the nitride spacer layer to produce insulating sidewall spacers over the first and second word line active area sidewall edges, the anisotropic etching leaving at least a portion of the nitride capping layer covering each of the first and second word lines, the portion of each nitride capping layer joining with one of the sidewall spacers to cover the first and second word line active area sidewall edges; d) providing an oxide layer over the sidewall spacers and capping layer; e) patterning and etching the oxide layer selectively relative to the nitride capping layer and sidewall spacers to define a contact opening to the active area, the contact opening overlapping with at least one nitride capping layer portion on one of the word lines; and f) providing an electrically conductive plug within the contact opening. A non-volatile memory array is disclosed.

REFERENCES:
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5270240 (1993-12-01), Lee
patent: 5427966 (1995-06-01), Komori et al.
patent: 5484741 (1996-01-01), Bergemont

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