Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1998-04-06
2000-02-15
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438710, 438712, H01L 21283
Patent
active
060252731
ABSTRACT:
A method is achieved for fabricating small contact holes in an interlevel dielectric (ILD) layer for integrated circuits. The method increases the ILD etch rate while reducing residue build-up on the contact hole sidewall. This provides a very desirable process for making contact holes small than 0.25 um in width. After depositing the ILD layer over the partially completed integrated circuit which includes patterned doped first polysilicon layers, a second polysilicon layer is deposited and doped with carbon by ion implantation. A photoresist mask is used to etch openings in the carbon doped polysilicon layer to form a hard mask. The photoresist is removed, and the contact holes are plasma etched in the ILD layer while free carbon released from the hard mask, during etching, reduces the free oxygen in the plasma. This results in an enhanced fluorine (F.sup.+) etch rate for the contact holes in the ILD layer and reduces the residue build-up on the sidewalls of the contact holes. The hard mask is anneal in O.sub.2 to form an oxide layer and any surface carbon is removed in a wet etch. Reliable metal plugs can now be formed by depositing a barrier layer, such as titanium (Ti) or titanium nitride (TiN) and a metal such as tungsten (W) and etching back or chemical/mechanical polishing back to the oxide layer.
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Chen Chao-Cheng
Tao Hun-Jan
Tsai Chia-Shiung
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
Utech Benjamin L.
Vinh Lan
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