Method for manufacturing crown-shaped capacitors for dynamic ran

Details Method for manufacturing crown-shaped capacitors for dynamic ran Method for manufacturing crown-shaped capacitors for dynamic ran

1997-04-11

1998-07-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438631, 438649, H01L 218242

Patent

active

057803382

ABSTRACT:
A method for manufacturing crown-shaped stacked capacitors on dynamic random access memory using a single photoresist mask to make the node contacts and capacitor bottom electrodes was achieved. After forming the FET gate electrodes from a first polysilicon layer and the bit lines from a second polysilicon layer, a thick planar BPSG and a hard mask composed of polysilicon or silicon nitride is deposited. Openings are etched in the hard mask and partially into the BPSG. Sidewall spacers, composed of Si.sub.3 N.sub.4 or TEOS oxide, are formed in the openings and a special selective high density plasma etch and the etchant gas mixture of O.sub.2, CHF.sub.3, CF.sub.4, CO, C.sub.4 F.sub.8, and Ar is used to form the node contact openings in the BPSG to the FETs. A conformal third polysilicon layer is then deposited and a second masking material is used to define the bottom electrodes having a crown-shape in the BPSG openings. After removing the hard mask, the second masking material, and the BPSG between electrodes, an interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped fourth polysilicon layer is deposited to form the top electrodes and to complete the crown-shaped stacked capacitors.

REFERENCES:
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J. Givens et al. "Selective Dry Etching in a High Density Plasma for a O Seem Complementary Metal-Oxide-Semiconductor Technology", J. Vac Sci Technol, B 12(1), Jan./Feb. 1994, pp. 427-432.

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