Method to increase the resistance of a polysilicon load resistor

Details Method to increase the resistance of a polysilicon load resistor Method to increase the resistance of a polysilicon load resistor

1996-12-27

1998-02-24

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438385, 438659, H01L 218244

Patent

active

057211663

ABSTRACT:
A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.

REFERENCES:
patent: 5146107 (1992-09-01), Matsuoka et al.
patent: 5236856 (1993-08-01), Chan et al.
patent: 5424239 (1995-06-01), Sweeney
patent: 5461000 (1995-10-01), Liang
patent: 5554552 (1996-09-01), Chi
patent: 5554554 (1996-09-01), Bastani et al.
patent: 5622884 (1997-04-01), Liu

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