Integrated circuit memory devices having main and section row de

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36523006, 3652385, G11C 700

Patent

active

058598022

ABSTRACT:
Integrated circuit memory devices having improved burst mode operation include an array of memory cells arranged as a plurality of normal rows of memory cells electrically coupled to respective normal section word lines (SWL) and a plurality of redundant rows of memory cells electrically coupled to respective redundant section word lines (RSWL). A first normal section row decoder is also provided. The first normal section row decoder has first inputs electrically coupled to a plurality of burst address selection lines (Ci, Cj, Ck and Cl), a second input electrically coupled to a normal main word line (MWL) and outputs electrically coupled to a plurality of the normal section word lines (SWL1-4). A first redundancy section row decoder is also preferably provided. The first redundancy section row decoder has first inputs electrically coupled to the plurality of burst address selection lines, a second input electrically coupled to a redundant main word line (RMWL) and outputs electrically coupled to a plurality of the redundant section word lines (RSWL1-4). Normal main row decoder circuitry is also provided and is responsive to a most significant portion of a row address. When the appropriate portion of a predetermined row address is provided, the main row decoder circuitry drives the corresponding normal main word line. Moreover, redundant main row decoder circuitry is provided and is responsive to the most significant portion of the row address. When the appropriate portion of a predetermined row address is provided, the redundant main row decoder circuitry drives the corresponding redundant main word line.

REFERENCES:
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5428573 (1995-06-01), Watanabe
patent: 5502676 (1996-03-01), Pelley, III et al.
patent: 5621690 (1997-04-01), Jungroth et al.
patent: 5737269 (1998-04-01), Fujita

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuit memory devices having main and section row de does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit memory devices having main and section row de, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory devices having main and section row de will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1521894

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.