Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-05
1999-11-09
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438257, 438229, 438304, 438367, H01L 21336
Patent
active
059813415
ABSTRACT:
A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.
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A 0.67 um2 Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) For 3V-only 256Mbit NAND EEPROMS, pp. 3.6.1-3.6.4, International Electronic Devices Meeting, Sponsored by IEEE, 1994.
Hui Angela T.
Kim Unsoon
Liu Yowjuang W.
Sun Yu
Advanced Micro Devices
Duong Khanh
Jr. Carl Whitehead
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