Silicon-germanium devices for CMOS formed by ion implantation an

Details Silicon-germanium devices for CMOS formed by ion implantation an Silicon-germanium devices for CMOS formed by ion implantation an

1996-09-18

1999-03-09

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438299, 438528, H01L 21336

Patent

active

058799966

ABSTRACT:
A PMOS transistor is formed in a CMOS integrated circuit, having a Si.sub.1-x Ge.sub.x /Si heterojunction between the channel region and the substrate. The method is applicable to large volume CMOS IC fabrication. Germanium is implanted into a silicon substrate, through a gate oxide layer. The substrate is then annealed in a low temperature furnace, to form Si.sub.1-x Ge.sub.x in the channel region.

REFERENCES:
patent: 4394181 (1983-07-01), Nicholas
patent: 5145794 (1992-09-01), Kase et al.
patent: 5254484 (1993-10-01), Hefner et al.
patent: 5298435 (1994-03-01), Aronowitz et al.
patent: 5312766 (1994-05-01), Aronowitz et al.
patent: 5426069 (1995-06-01), Selvakumar et al.
M. Berti, et al., "Composition and Structure of Si-Ge Layers Produced by Ion Implantation and Laser Melting", J. Mater. Res., vol. 6, No. 10, pp. 2120-2126, Oct. (1991).
M. Berti, et al., "Laser Induced Epitaxial Regrowth of Si.sub.1-x Ge.sub.x /Si Layers Produced by Ge Ion Implantation", Appl. Surf. Sci. vol. 43, pp. 158-164, Jan. (1989).
B. T. Chilton, et al., "Solid Phase Epitaxial Regrowth of Strained Si.sub.1-x Ge.sub.x /Si Strained-layer Structures Amorphized by Ion Implantation", Appl. Phys. Lett., vol. 54, No. 1, pp. 42-44, Jan. (1989).
Vandebroek, Bernard S. Myerson, et al., "SiGe-Channel Heterojunction p-MOSFET's", IEEE Trans. on Electron Devices, vol. 41, No. 1, pp. 90-100, (Jan. 1994).
D. C. Paine, et al., "The Growth of Strained Si.sub.1-x Ge.sub.x Alloys on (100) Silicon Using Solid Phase Epitaxy", J. Mater Re., vol. 5, No. 5, pp. 1023-1031, May (1990).
R. People, et al., "Calculation of critical layer thickness versus Lattice Mismatch for Si.sub.1 -xGe.sub.x /Si Strained-layer Heterostructures", Appl. Phys. Lett., Aug. (1985), pp. 322-324, Erraltum.
G.A. Garcia et al, "High Quality CMOS in Thin (100nm) Silicon on Sapphire", IEEE Elect. Device Lett, vol. 9, No. 1, pp. 32-34, (Jan. 1988).
D. K. Nayak, K. L. Wang, et al., "High Performance GeSi Quantum-Well PMOS on SIMOX", Proc. Int. Electron Device Meeting, San Francisco, pp. 777-780, (Dec. 1992).

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