Method for manufacturing a semiconductor device with self-aligne

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438738, H01L 218234

Patent

active

060487615

ABSTRACT:
A self-aligned protection diode is formed at the first polycrystalline silicon level, thereby enabling in-process charging damage protection while reducing the layout area. The self-aligned protection diode is formed by providing an etch stop layer having an arcuate portion with different etching characteristics than horizontal portions, isotropically etching the arcuate portion to form a through hole exposing a side surface of a polycrystalline silicon layer and the underlying semiconductor substrate, ion implanting impurities to form the protection diode, and filling the through hole with a metal interconnecting the side surface of the polycrystalline silicon layer with the vertically self-aligned protection diode.

REFERENCES:
patent: 5587598 (1996-12-01), Hatanaka
patent: 5602410 (1997-02-01), Schwalke et al.
patent: 5641991 (1997-06-01), Sakoh
patent: 5672895 (1997-09-01), Iida et al.
patent: 5705437 (1998-01-01), Wu et al.
patent: 5710076 (1998-01-01), Dai et al.
patent: 5808365 (1998-09-01), Mori
patent: 5899749 (1999-05-01), Becker et al.
Zheng et al., "A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient", 1996 1.sup.st International Symposium on Plasma Process-Induced Damage (IEEE Cat. No. 96TH8142), May 1996, pp. 27-29.
H.C. Shin et al., "Thin gate oxide damage due to plasma processing", Semiconductor Science and Technology, Apr. 1996, vol. 11, No. 4, pp. 463-473.
H. Shin et al., "Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide", International Electron Devices Meeting 1993, IEEE Cat. No. 93CH3361-03, 1993, pp. 467-470.
M.C. Chang et al., "Degradation of MOS Transistor Characteristics by Gate Charging Damage During Plasma Processing", International Symposium on VLSI Technology, Systems, and Applications, IEEE Cat. No. 93TH0524-9, 1993, pp. 320-324.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for manufacturing a semiconductor device with self-aligne does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a semiconductor device with self-aligne, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor device with self-aligne will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1176026

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.