Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-05-21
2000-08-08
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438234, 438241, 438151, 438152, 438153, 438329, 438330, 438309, 438953, 438668, H01L 218234
Patent
active
061001260
ABSTRACT:
A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques. A second metal interconnection is then formed and completes the static random access memory (SRAM) cell.
REFERENCES:
patent: 5780326 (1998-07-01), Dennison et al.
patent: 5821160 (1998-10-01), Rodriguez et al.
Chen Min-Liang
Chu Chih-Hsun
Gurley Lynn A.
Mosel Vitelic Inc.
Niebling John F.
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