Method for forming high voltage and low voltage transistors on t

Details Method for forming high voltage and low voltage transistors on t Method for forming high voltage and low voltage transistors on t

1997-12-11

2000-01-04

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, H01L 218238

Patent

active

060109297

ABSTRACT:
A process for forming high voltage and low voltage transistors on the same substrates includes first forming a poly gate (16) over layer gate oxide (10) on a substrate (12). An LDD implant is then performed, followed by the formation of a nitride cap (30) over the gate (16). The cap (30) is not disposed over gate electrodes associated with low voltage transistors. Thereafter, the source/drain implant is performed which forms source/drain regions (40) and (42). The cap (30) prevents the introduction of dopants into the gate electrode (16) during the source/drain implant step. This effectively increases the gate oxide width due to a larger depletion region at the oxide/polysilicon gate boundary as compared to the low voltage transistors with the higher dopant levels and the gate electrode.

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