Method and device for setting a plurality of test modes using ex

Details Method and device for setting a plurality of test modes using ex Method and device for setting a plurality of test modes using ex

1997-10-17

2000-09-12

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

324763, 324765, G01R 3128

Patent

active

061192538

ABSTRACT:
A method for setting test modes in a semiconductor ship and a device suitable for the method are provided. In the method, a power voltage is externally applied to the semiconductor chip. A predetermined signal is applied to an arbitrary selected external pin of the semiconductor chip. A first-state signal is applied to the test pin and a second-state signal is applied to the test pin a predetermined time later. The signal applied to the external pin is latched by the first-state signal applied to the test pin. The second-state signal applied to the test pin, a predetermined signal output when the first-state signal applied to the test pin is shifted to the second-state signal, and the latched signal are logically combined and the combined signal is output.

REFERENCES:
patent: 5198758 (1993-03-01), Iknaian et al.
patent: 5406567 (1995-04-01), Ogawa
patent: 5528162 (1996-06-01), Sato
patent: 5732209 (1998-03-01), Vigil et al.

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