Write driver circuit of an unmuxed bit line scheme

Details Write driver circuit of an unmuxed bit line scheme Write driver circuit of an unmuxed bit line scheme

2008-08-01

2010-10-26

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230060

Reexamination Certificate

active

07821845

ABSTRACT:
A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver.

REFERENCES:
patent: 5278788 (1994-01-01), Nomura
patent: 5745432 (1998-04-01), McClure
patent: 5841730 (1998-11-01), Kai et al.
patent: 6104666 (2000-08-01), Kumar
patent: 7596040 (2009-09-01), Tokito
patent: 6-195977 (1994-07-01), None
patent: 2004-348836 (2004-12-01), None
patent: 2003-23334 (2003-03-01), None

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