Writable logic array

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Patent

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Details

364716, 307465, G11C 700

Patent

active

047962291

ABSTRACT:
A writable logic array includes a first matrix (12,38) of gate elements. Program lines (16) connect the first array (12,38) with a second matrix (18,40) of gate elements. A plurality of switches (22), one for each program line (16), selectively couple or decouple the program lines (16) to the second matrix (18,40). Switches (22) are in turn controlled by a volatile memory (32), into which instructions may be written at the time the system into which the array is incorporated is booted up.

REFERENCES:
patent: 4488230 (1984-12-01), Harrison

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