Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-03
2006-10-03
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S724000, C714S718000
Reexamination Certificate
active
07117413
ABSTRACT:
A wrapped core linking module for accessing system on chip test includes a link control register that stores link control configuration between cores in a scan path of a system on chip according to control signals applied from an outside boundary. A link control register controller controls a shift and update link configuration by activating the link control register. A switch switches the scan path between wrapped cores based on the link control configuration of the link control register. An output logic connects the link control register to a test data out (TDO) of the chip in case of testing on chip or cores of system on chip.
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Benabdenbi, M.; Maroufi, W.; Marzouki, M.;Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings13-16 Mar. 2001 pp. 150-155 Digital Object Identifier 10.1109/DATE.2001.915016 □□.
Lee Hyung Su
Park Chang Won
Park Sung Ju
Song Jae Hoon
Alphonse Fritz
Greenblum & Bernstein P.L.C.
Korea Electronics Technology Institute
Lamarre Guy
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