Wiring substrate with thermal insert

Details Wiring substrate with thermal insert Wiring substrate with thermal insert

1999-08-16

2001-11-13

Picard, Leo P. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S765000, C361S807000, C361S809000, C174S250000, C174S255000, C257S737000, C257S738000, C257S782000, C257S783000, C228S124500, C428S210000

Reexamination Certificate

active

06317331

ABSTRACT:

BACKGROUND OF THE INVENTION
A major problem facing manufacturers of wiring substrates, such as printed wiring boards (“PWBs”), chip carriers, and VLSI substrates, is the management of thermal expansion stresses between the materials of the substrate, in the case of a laminated substrate, and between the materials of the substrate and components mounted on the substrate.
Thermal stresses can arise in at least two situations. One situation is when a thermal gradient is present. A higher temperature in one area of the substrate, such as underneath a heat source, can cause thermal expansion relative to a cooler area of the substrate, even if the substrate is made of a single material. The effects of this situation can often be mitigated by slowly changing temperature, thus lowering the thermal gradient.
A second situation is when materials with different coefficients of thermal expansion (“CTE”) are used. One material then expands and contracts at a different rate (typically expressed as a dimensionless coefficient, e.g. mm/mm, per degree of temperature) than the other as the temperature changes. Differential CTEs can cause problems regardless of the rate at which the materials are heated or cooled. If the materials are bonded or otherwise attached together, thermal stress is generated when the temperature changes. This stress can result in deformation (warping) or even fracture of the material, in order to relieve the stress.
For example, PWBs are typically formed by laminating several layers of different materials together. Conductive layers, such as copper layers patterned according to a desired wiring layout, are typically separated by, and laminated to, dielectric layers that provide electrical insulation between the conductive layers. The dielectric layers are typically polymeric resins, such as epoxy resins, including fiber-reinforced resins. The dielectric layers often have a CTE of about 50-70 ppm/° C., while the metals used in the conductive layers have a CTE of about 16-17 ppm/° C. Thus, a heat source placed on a PWB or similar wiring substrate can create thermal stress.
The increased complexity of contemporary integrated circuits affects the problems arising from thermal stress in many ways. First, the high device count on very-large-scale integrated circuit (VLSI”) chips often means a single chip will generate more heat compared to a chip with a lower device count. The shrinking dimensions of the devices on the chips mean that the heat is often concentrated in a smaller area. Some ICs generate over 10 W/cm
2
. The shrinking dimensions also mean that the traces on the chip are finer pitch and the contact pads on the chip also have finer pitch, not to mention that the number of contact pads has substantially increased. Finally, the overall dimensions of VLSI chips have increased in many cases. The increased dimensions result in a greater total expansion or contraction, which can lead to higher thermal stress.
A variety of technologies have been developed to address the finer contact pitch and increased number of contacts. Examples include ball-grid arrays (“BGAs”), which are packaged chips with an array of bumps, typically solder dots, on one surface of the package. The package may include a chip carrier or lead frame, with the actual semiconductor chip bonded to the carrier and the electrical contacts brought from the IC chip to the balls of the BGA. Another example are known as “flip chips”, which are similar to BGA packages in that bumps, typically of solder, eutectic, or conductive adhesive, are formed over contact pads on the IC chip. The chip is then “flipped” onto a wiring substrate and bonded. Flip-chip is usually reserved to describe a type of direct chip attach, even though it is very similar to the packaged BGA process.
Unfortunately, the IC package or flip chip may be made of a material, such as plastic, ceramic, or semiconductor, with a different CTE than any of the materials in the wiring substrate. To complicate matters, the finer pitch of the contact array typically means a finer wiring pattern must be used on the wiring substrate. The finer wires are not as strong as wider wires would be, and thus are more susceptible to breakage when subjected to stress. Similarly, if a shear stress develops between the IC and the substrate, a smaller solder ball will have less strength to resist the stress (including work hardening), and may fail at the joint, or may crack. A particularly insidious aspect of such failures is that an electrical contact may be established at one temperature, and not at another, as thermal expansion and contraction brings the cracked or broken halves of the electrical path together and apart.
One technique that has been used to improve the reliability of BGAs attached to a PWB is to underfill the BGA. Underfilling typically involves applying a liquid to an edge or edges of the BGA, the liquid being wicked under the BGA by capillary action. The liquid then solidifies, or is solidified, as through a polymerization process for example, to “glue” the BGA to the surface of PWB. The CTE of the underfill material is typically chosen to match the CTE of the material the balls of the BGA are made of, typically a solder. These CTEs are matched to reduce the chance that the underfill material will pop the BGA off the surface of the wiring substrate, break a solder joint, or fracture a solder ball. Unfortunately, the CTE of the underfill material might not be a good match for the CTE of the integrated circuit or the CTE of the PWB.
Another technique that has been used to minimize the differences in CTEs between an integrated circuit and a wiring substrate is to incorporate a CTE matching layer within the laminated structure of the PWB. The CTE matching layer generally provides a CTE that is closer to the CTE of the integrated circuit, which typically includes a silicon chip. The CTE matching layer is typically a sheet of low CTE material, such as 64% Fe-36% Ni (commonly known as “INVAR”™) or molybdenum, clad or plated with copper. The laminate layer is typically provided as a foil that is patterned according to a desired wiring pattern or is largely unpatterned for use as a ground plane or the like. A copper-INVAR-copper foil is commonly called a “CIC” foil. These foils generally extend throughout the entire laminate layer. Unfortunately, low CTE material such as CIC or copper-molybdenum is relatively expensive, compared to a standard copper foil.
Therefore, it is desirable to reduce the failures caused by thermal stress in wiring substrates and in assemblies of integrated circuits and wiring substrates. It is further desirable that the reduction of failures be achieved without inducing other undesirable consequences.
SUMMARY OF THE INVENTION
The present invention provides wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region proximate to the integrated circuit. In one embodiment, the thermal expansion reduction insert extends a selected distance from the edge or edges of the integrated circuit attachment area, while in another embodiment it stops a selected distance from the edge or edges of the integrated circuit attachment area. In still another embodiment, the thermal expansion area is essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly.
In a specific embodiment, the wiring substrate is a laminated printed wiring board with the thermal expansion reduction insert in a layer proximate to an outer layer to which the integrated circuit is joined (mounted). In a further embodiment the thermal stress reduction insert is a CIC insert or a c

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