Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-22
2002-03-12
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S430000, C438S453000, C438S701000
Reexamination Certificate
active
06355515
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a wiring structure of a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
As semiconductor devices become more highly integrated or the speed thereof increases, a multi-layer wiring structure is required. Accordingly, it is important to secure an alignment margin in a photolithography process for reducing the pitch of metal wiring or succeeding wiring. It is necessary to increase the flatness of an insulating film for insulating the metal wiring in order to reduce the pitch of the metal wiring or to secure the alignment margin.
A process of planarizing the insulating film is necessary for increasing the flatness of the insulating film. For example, one such exemplary process comprises a method of forming an insulating film and polishing the insulating film globally by a chemical mechanical polishing (CMP) method. The process of planarizing the insulating film using the CMP method is essential for securing a processing margin and process stabilizing in manufacturing a multi-layer wiring structure.
FIG. 1
schematically shows a sectional view of the wiring structure of a conventional semiconductor device.
To be specific, the conventional wiring structure will be described, taking a static random access memory (SRAM) device in which the CMP method is used as a planarizing method, as an example. A first insulating film
31
insulates a lower structure such as a drain or source region
15
formed on a semiconductor substrate
10
, a gate electrode
23
, and a V
CC
line
40
from the metal wiring, for example, a first wiring
61
. The first insulating film
31
is planarized by the CMP method in order to increase the flatness.
A groove of a second insulating film
35
formed on the first insulating film
31
is filled with the first wiring
61
. Namely, the first wiring
61
is formed by a damascene process. A conductive stud
63
formed in a contact hole through the second insulating film
35
and the first insulating film
31
contacts the drain or source area
15
. The first wiring
61
and the stud
63
are formed by filling the groove or the contact hole with a conductive film and polishing the conductive film by the CMP method. It is essential for securing the processing margin or the multi-layer wiring structure in a succeeding process to form the first wiring
61
or the conductive stud
63
by planarizing the conductive film by the CMP method.
However, the conductive film may be over polished when it is polished by the CMP method and the first wiring
61
or the conductive stud
63
can be excessively etched by this over polishing phenomenon. The first wiring
61
operates as a word line or a V
SS
line in the semiconductor device. Therefore, the excessive etching can reduce the cross sectional area of the first wiring
61
, thus increasing the resistance of the first wiring
61
or cause a short of the first wiring
61
. The increase of the resistance of the first wiring
61
can decrease the operating speed of the semiconductor device or cause misoperation of the semiconductor device. The conductive stud
63
is connected to second wiring formed on the first wiring
61
.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a wiring structure of a semiconductor device in which it is possible to prevent an increase in the resistance of the wiring or a short in the wiring by preventing the wiring from being excessively etched when a planarizing method such as a CMP method is used.
It is another objective of the present invention to provide a method for manufacturing the wiring structure of the semiconductor device by which it is possible to prevent the increase in the resistance of the wiring or the short in the wiring by preventing the wiring from being excessively etched when a planarizing method such as a CMP method is used.
Accordingly, to achieve the first objective, there is provided a wiring structure of a semiconductor device, comprising a body and a protrusion, formed of a conductive material in a first insulating film on a semiconductor substrate. The body is preferably a polygonal column or a hemispherical column. The protrusion is formed of a conductive material in a second insulating film formed on the first insulating film and connected to the upper surface of the body The protrusion is formed to have a width narrower than that of the body, and has a planarized upper surface.
The first insulating film is formed of a material having an etching rate greater than that of the second insulating film. A conductive stud insulated from the wiring by the first insulating film and the second insulating film, connected to the semiconductor substrate, and having a planarized surface having the same height as the planarized surface of the wiring is further comprised.
The conductive material is one selected from a group consisting of tungsten, aluminum, tungsten alloy, and aluminum alloy. The wiring structure can be applied to a semiconductor device such as an SRAM device. At this time, the wiring is used as a V
SS
line or a word line.
To achieve the second objective, there is provided a method for manufacturing the wiring structure of a semiconductor device. In the method, a first insulating film is formed on a semiconductor substrate. A second insulating film having an etching ratio less than that of the first insulating film is formed on the first insulating film. A second insulating film pattern having an aperture exposing some of the surface of the first insulating film is formed by patterning the second insulating film. A trench having a width greater than the width exposed by the aperture is formed by patterning some of the first insulating film exposed by the aperture. A conductive film for filling the trench and the aperture is formed on the second insulating film pattern. A protrusion and a body having a width greater than the width of the protrusion are respectively formed in the aperture and in the trench by planarizing conductive film.
In forming the trench, a trench having a width greater than the width exposed by the aperture is formed by performing a dry etching or a wet etching process in a condition in which the etching rate of the first insulating film is greater than that of the second insulating film pattern. In forming the conductive film, the conductive film is preferably formed of a material selected from a group consisting of tungsten, aluminum, tungsten alloy, and aluminum alloy.
The forming of a contact hole exposing some of the semiconductor substrate by sequentially patterning the second insulating film pattern and the first insulating film is further comprised before forming the conductive film. The contact hole is filled together with the trench and the aperture in the step of forming the conductive film. A conductive stud is formed in the contact hole by planarizing the conductive film filling the contact hole in the planarizing of the conductive film. The conductive film is polished by a chemical mechanical polishing (CMP) method in the planarizing of the conductive film.
Such a wiring structure can be applied to a semiconductor device such as an SRAM device. At this time, the wiring is used as a V
SS
line or a word line.
According to the present invention, it is possible to prevent the excessive etching of the wiring and to pattern the wiring using a planarizing method such as the CMP method. Accordingly, it is possible to prevent the increase in the resistance of the wiring or the short in the wiring. Also, it is possible to use a multilayer wiring structure, to secure a succeeding process margin, and stabilize a process.
REFERENCES:
patent: 5225376 (1993-07-01), Feaver et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 5851928 (1998-12-01), Cripe et al.
patent: 5904576 (1999-05-01), Yamaha et al.
patent: 5920761 (1999-07-01), Jeon
patent: 5989623 (1999-11-01), Chen et al.
patent: 6008129 (1999
Kim Gyu-chul
Moon Jae-hwan
Bowers Charles
Cantor & Colburn LLP
Kebede Brook
Samsung Electronics Co,. Ltd.
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