Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-20
2007-02-20
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
10790906
ABSTRACT:
A wireless integrated circuit test method and system is presented. The invention allows testing of one or more integrated circuits configured with a wireless interface and a test access mechanism which controls input of test data received over a wireless connection from a test station to test structures which test functional blocks on the integrated circuit. Via the wireless connection, multiple integrated circuits or similarly equipped devices under test can be tested simultaneously. The invention also enables concurrent testing of independently testable functional blocks on any given integrated circuit under test.
REFERENCES:
patent: 6112067 (2000-08-01), Seike et al.
patent: 6189120 (2001-02-01), Akram
patent: 6412086 (2002-06-01), Friedman et al.
patent: 6807644 (2004-10-01), Reis et al.
Tu Christine T.
Verigy Pte, Ltd.
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