Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-17
2003-01-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06510540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to a signal processing system and in particular to an improved method for performing cross-talk analysis. Still, more particularly, the present invention discloses a novel method to reduce pessimism in cross-talk analysis of digital chips.
2. Description of Related Art
In digital chips, excessive cross-talk noise on a victim net can lead to logic failure. A victim net as depicted in the prior art, may be a simple, point-to-point circuit comprised of a source and a sink, or it may be a more complex circuit. When sufficient cross-talk noise is injected onto a net, its logic state will change and any “down-stream” logic circuits will then sense the errant logic state. If at some point downstream the corrupted logic state is sampled (or clocked) into a latch, then the logic state of the digital circuit is incorrect and the circuit has failed. It is therefore desirable to be able to simulate such phenomena and correct the circuit design prior to the time and cost of actually manufacturing the circuit. The common approach for determining potential cross-talk-induced failures is to first simulate the peak noise induced at the victim sink pin by each of the neighboring aggressor nets. Because the exact times at which these noises occur cannot be precisely determined, the common approach is to combine the noise of each aggressor net as if these peaks were temporally aligned. And finally, if this worst case combination exceeds the noise tolerance of the sink pin, the common approach tags the net as a failing net. This procedure is clearly pessimistic because in many cases, not all aggressor nets can switch simultaneously nor does the maximum noise occur when the downstream latch samples the net. An aggressor net as depicted in the prior art, may be a simple, point-to-point circuit comprised of a source and a sink, or it may be a more complex circuit. Pessimism in cross talk analysis of digital circuits is the result of determining that the worst-case noise is the combination of the peak noise from all possible noise sources, i.e. any potential aggressor nets. Therefore, it would be advantageous to have an improved method and apparatus for reducing pessimism in simulating circuits.
SUMMARY OF THE INVENTION
The present invention reduces pessimism in a victim net by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. First, victim sensitivity windows and aggressor switching windows are determined using results from timing analysis and circuit simulation of coupled-interconnect noise.
The aggressor switching window (ASW) is a continuous time interval that repeats every cycle of the aggressor clock (CLK A). This time interval is the interval when the peak noise created by the aggressor can develop at the victim sink.
The victim sensitivity window (VSW) is a continuous time interval that repeats every cycle of the victim clock (CLK V). This time interval is the time when the downstream errant data can cause the receiving latch to sample incorrectly.
Once aggressor switching windows and the victim sensitivity window are found, further timing analysis is performed to determine whether any overlap between the various aggressor switching windows and the victim sensitivity window exists. The overlap of the timing windows will be the basis for restricting which aggressor circuits contribute to the total noise. Specifically, if the timing windows of two aggressor nets do not overlap, they will be considered as never both contributing to the total noise. Likewise, if an aggressor timing window does not overlap a victim sensitivity window, it will be considered to never contribute to the total noise. The total noise will then be determined as the worst possible noise resulting from all possible combinations of aggressor circuits whose timing windows meet the overlap criteria.
The technique employed in determining maximum noise effectuates a reduction in pessimism. If a given aggressor net has a corresponding aggressor switching window that does not occur within a given victim sensitivity window, its peak noise will not be considered in circuit failure analysis, thereby reducing the number of false fails for a circuit design. Pessimism may be reduced in synchronous as well as asynchronous circuits using the techniques disclosed in this invention.
REFERENCES:
patent: 4135161 (1979-01-01), Torrieri
patent: 5555506 (1996-09-01), Petschauer et al.
patent: 5568395 (1996-10-01), Huang
patent: 5983006 (1999-11-01), Carlson et al.
patent: 6128769 (2000-10-01), Carlson et al.
Krauter Byron Lee
Mehrotra Sharad
Saxman Jonathan Humphrey
Villarrubia Paul Gerard
Widiger David J.
Carwell Robert M.
Dinh Paul
Nichols Michael R.
Smith Matthew
Yee Duke W.
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