Multi-metal layer circuit

Details Multi-metal layer circuit Multi-metal layer circuit

2000-07-14

2003-01-14

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S737000, C257S750000, C029S852000

Reexamination Certificate

active

06507118

ABSTRACT:

BACKGROUND
The disclosures herein relate generally to electronic packages and more specifically, to ball grid array flip chip electronic packages with chip scale interposers.
Flip chip electronic packages continue to gain popularity in the integrated circuit packaging industry. Flip chip electronic packages offer smaller form factors than other types of packages, lower cost in high routing density applications, and excellent electrical performance. Furthermore, an electronic package can be tested in a suitable test apparatus far more easily than a fragile bare die can be tested. Attributes such as these are driving the increase in popularity of flip chip electronic packages.
Presently, flip chip electronic packages are geared toward high performance applications. Flip chip electronic packages for these types of applications typically use multilayer substrates that provide numerous routing layers and reference voltage layers. These types of packages are effective, but are too costly to be used for mainstream applications.
In general, attaching a flip chip electronic package, rather than a bare flip chip die, to a printed circuit board is preferred. A key reason for such a preference is that when a bare die is attached directly to the printed circuit board in a flip chip format, there is a large thermal expansion differential between the die and printed circuit board. The thermal expansion differential contributes to poor thermal cycle fatigue reliability.
To limit the adverse affects of the thermal expansion differential, an underfill material is applied between the die and the printed circuit board. The underfill material helps to distribute stress more evenly, thus reducing the stress on associated solder balls. However, once the underfill is applied, the die cannot be cost-effectively removed from the printed circuit board. Thus, if the die, printed circuit board, or an interconnection therebetween proves to be defective, the entire printed circuit board assembly is typically discarded. As the die and any other components already attached to the printed circuit board are typically expensive, it is undesirable to discard printed circuit board assemblies.
Another limitation of conventional flip chip packages are that they are easily implemented into the existing supply chain industry of the electronics industry. The direct attachment of unpackaged flip chip dies to printed circuit boards do not fit board assemblers capabilities. In particular, the assembly of unpackaged flip chip dies requires an underfill step. This underfill step is timely to complete and requires that an entire printed circuit assembly be discarded if the underfilled die is defective.
Flip chip electronic packages include a flip chip die attached to an interposer circuit. A flip chip electronic package can be cost effectively attached to and removed from a printed circuit board. In such a configuration, the flip chip electronic package can be readily removed from the printed circuit board, if needed. This allows for reworking of the printed circuit board assembly such that the entire printed circuit board assembly does not need to be discarded if a defect in the flip chip electronic package or its interconnection to the printed circuit board is detected.
U.S. Pat. Nos. 5,798,567, 5,777,386, 5,686,764 and 5,616,958 disclose various embodiments of large scale flip chip electronic packages. Each one of the disclosed embodiments includes a flip chip die mounted on a substrate such as an interposer circuit. By large scale, it is meant that the interposer circuit has an area substantially greater than a mounting surface area of the flip chip die. These types of electronic packages provide for signal and power routing in high density applications and provide superior electrical performance relative to other types of electronic packages, such as wire bond electronic packages. However, the benefits associated with the small form factor of chip scale packages is not captured by large scale flip chip electronic packages.
U.S. Pat. No. 5,637,920 discloses an embodiment of a flip chip electronic package including a flip chip die mounted on an interposer circuit having a multilayer core. Interposer circuits having multilayer cores provide for increased routing density in a relatively small form factor by routing traces on a plurality of conductive layers. However, interposer circuits having multilayer cores are generally more expensive to fabricate relative to interposer circuits having a single layer dielectric core.
U.S. Pat. Nos. 5,909,010 and 5,866,949 disclose various embodiments of wire bond flip chip electronic packages having a chip scale package (CSP) format. In wire bond CSP flip chip electronic packages, such as those disclosed in the reference patents, the packages include a flip chip die mounted on an interposer circuit. The interposer circuit has a larger area than the flip chip electronic device to enable conductive lead connections to be formed around the respective perimeter edges of the interposer circuit and die. Relative to BGA flip chip electronic packages, the orientation of the conductive leads results in a larger form factor and a reduced level of electrical performance.
Various embodiments of interposer circuits with dielectric cores are known. U.S. Pat. No. 5,346,861 discloses an interposer circuit suitable for lead bonded flip chip electronic packages. A key limitation of lead bonded flip chip electronic packages is that considerable time is required to bond all of the leads. U.S. Pat. Nos. 5,491,303 and 5,352,926 disclose respective interposer circuits having vias including respective bonding pads on opposing surfaces of a dielectric core. The formation of electrically conductive vias is expensive relative to non-conductive passages extending through a dielectric core. Furthermore, in high density applications such as flip chip CSP's, a solder mask layer must be formed on the opposing surfaces of the dielectric core to contain solder during reflow.
Therefore, for flip chip electronic packages to be seen as an acceptable packaging configuration for mainstream applications, what is needed is a flip chip electronic package that can be cost effectively assembled and tested by a package assembly subcontractor and that can be cost effectively attached to a printed circuit assembly by a board assembly contractor.
SUMMARY
Embodiments of electronic packages according to the present invention will provide an effective balance between cost, electrical performance, routing density and form factor. Furthermore, such embodiments will also provide for cost effective integration into existing assembly and testing operations used for conventional types of packaging solutions.
An embodiment of a chip scale electronic package, accordingly, includes an interposer circuit having a dielectric core with an array of contact members attached to the dielectric core. Each contact member includes a first interconnect surface accessible from a first side of the dielectric core and a second interconnect surface accessible from a second side of the dielectric core. A flip chip electronic device including an array of bond pads on a mounting surface of the electronic device A conductive element is attached to the first interconnect surface of each contact member. Each bonding pad is substantially aligned with a respective one of the first interconnect surfaces of the interposer circuit. Each bonding pad is electrically connected to the corresponding conductive element.
The dielectric core preferably includes a layer of flexible polymeric material. The dielectric core of the present invention is preferably a single layer of polymeric material. In some embodiments of the present invention, a multilayer dielectric core including a plurality of layers of dielectric material or materials may be desirable. Examples of suitable flexible polymeric materials include polyimide and polyester.
One embodiment of contact members includes solder pads mounted on a surface of the dielectric core adjacent to a respective passage extendin

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