Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-06-07
1997-08-12
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
H01L 21265
Patent
active
056565178
ABSTRACT:
A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.
Other devices, systems and methods are also disclosed.
REFERENCES:
patent: 3926694 (1975-12-01), Cauge et al.
patent: 4644637 (1987-02-01), Temple
patent: 4914051 (1990-04-01), Huie et al.
patent: 4928155 (1990-05-01), Nakagawa et al.
patent: 5079602 (1992-01-01), Harada
Efland Taylor R.
Jones, III Roy C.
Kwon Oh-Kyong
Malhi Satwinder
Ng Wai Tung
Courtney Mark E.
Donaldson Richard L.
Dutton Brian K.
Franz Warren L.
Niebling John
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