Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-24
2002-04-09
Smith, Matthew (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S223000, C438S201000, C438S228000, C438S302000, C438S227000, C257S301000, C257S315000, C257S371000
Reexamination Certificate
active
06368914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a well structure in a NAND-type flash EEPROM (Electrically Erasable and Programmable Read Only Memory) device having a plurality of memory cell transistors for storing data and select transistors for selecting the memory cell transistors, and a method for fabricating the same.
2. Description of the Related Art
Semiconductor memory devices are largely divided into RAMs (Random Access Memories), such as DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), and ROMs (Read Only Memories). RAMs, also referred to as volatile memories because the stored data is destroyed with the passage of time, allow rapid data storage and data retrieval. ROMS, also referred to as nonvolatile memories because they retain data once it is entered, typically have slower data storage and data retrieval times.
Among ROMs, demands are increasing for EEPROMs, in which data is electrically programmed and erased. A flash EEPROM, which is electrically erasable at high speed without being removed from a circuit board, offers the advantages of a simple memory cell structure, cheap cost, and no need for a refresh signal to retain data.
Flash EEPROM cells are largely divided into two types: a NOR type EEPROM and a NAND type EEPROM. A NOR type EEPROM requires one contact in every two cells, which is not favourable for high scale integration, but has a large cell current, and is therefore capable of high-speed operation. A NAND type EEPROM is typically not capable of such high-speed operation due to a small cell current, but it shares one contact in a plurality of cells and thus is useful in realizing high scale integration. Therefore, the NAND flash EEPROM has attracted interest as a next generation memory device for use in digital still cameras and similar devices.
FIG. 1
is a sectional view of a cell array structure in a conventional NAND flash EEPROM, and
FIG. 2
is an equivalent circuit diagram of the cell array (see, Symposium on VLSI Circuits, 1990, pp. 105-106).
Referring to
FIGS. 1 and 2
, a single string is composed of a string select transistor SST for selecting a unit string, a ground select transistor GST for selecting the ground, and a plurality of memory cell transistors connected in series between the string select transistor SST and the ground select transistor GST. A bit line is connected to the drain of the string select transistor SST and a common source line CSL is connected to the source of the ground select transistor GST. One block is comprised of a plurality of strings connected in parallel to bit lines, and such blocks are symmetrically arranged with respect to a bit line contact.
A memory cell transistor includes a stack comprised of a floating gate
18
, formed on a semiconductor substrate
10
with interposition of a tunnel oxide film
16
, and a control gate
22
, formed on the floating gate
18
with interposition of an interlayer dielectric layer
20
. The floating gate
18
extends across an active region and across edge portions of the field regions at both sides of the active region, thus being isolated from a floating gate
18
in an adjacent cell. The control gate
22
is connected to that of an adjacent cell, forming a word line W/L.
A string select transistor requires no floating gate for storing data, and thus its floating gate
18
and control gate
22
are connected by a metal wire through a butting contact on a field region in a cell array. Therefore, the string select transistors act as MOS transistors electrically having a single-layer gate structure.
A general NAND flash EEPROM cell array as constituted above is produced by forming an n-well
12
on a p-substrate
10
and then forming a p-well
14
(pocket p-well
14
) inside the n-well
12
. A description of the cell operation will hereinbelow be described.
For programming a selected cell, 0V is applied to a bit line connected to the selected cell and a program voltage V
pgm
is applied to a word line connected to the selected cell, so that electrons are injected into the floating gate
18
due to the voltage difference between the channel and the control gate
22
of the memory cell transistor. Here, a pass voltage V
pass
is applied to unselected cells among a plurality of memory cells between the bit line and a ground node, to transfer data (i.e., 0V) applied to the selected bit line to the selected cell.
For example, when V
pgm
≡20V is applied to the word line of a selected cell A, V
pass
≡10V is applied to the word lines for the unselected cells in the string and to the string select transistor SST, 0V is applied to a selected bit line and a ground select transistor GST, and a program inhibit voltage V
pi
≡10V is applied to an unselected bit line, then electrons are injected into the floating gate
18
through the tunnel oxide film 16 from the p-well
14
due to the V
pgm
of the selected cell A.
For erasing a cell, that is, removing electrons stored in the floating gate
18
, an erase voltage V
erase
≡20V is applied to the p-well
14
, and 0V is applied to a word line connected to the selected cell. Electrons are removed from the floating gate and holes are injected thereinto by an electrical field generated by V
erase
which has a reverse polarity to that applied during the programming operation. To prevent V
erase
applied to the p-well
14
during the erasing operation from affecting a peripheral circuit, the memory cell array is formed in the pocket p-well
14
in the n-well
12
.
Data “0” or “1” is read from a selected cell according to the presence or absence of a current path through a selected cell, relying on the principle that the threshold voltage V
th
of the cell is changed to +1V when electrons are stored in the cell, while the threshold voltage Vth is changed to −3V when holes are stored in the cell.
To inhibit an unselected cell B connected to the unselected bit line and the selected word line from being programmed in the above NAND flash EEPROM cell array, a voltage V
pi
≡10V applied to the unselected bit line is directly induced to the channel of the unselected cell B by V
pass
applied to the unselected word line, thereby reducing the V
pgm
-induced electrical field and thus preventing F-N (Fowler-Nordheim) tunneling.
Because V
pi
is higher than the supply voltage V
cc
(3.3V or 5V), V
pi
should be produced by charge pumping using a capacitor. Charge pumping refers to generation of a required voltage by accumulating potential in a capacitor. As the required current capacity of the generated voltage increases, the capacitor requires a larger area. This increases the chip area required for forming the capacitor and increases the programming time, due to the time needed to charge the bit line voltage capacitor with V
pi
. Both of these effects are undesirable.
Accordingly, to avoid application of a higher voltage than V
cc
to the unselected bit line, a method has been suggested in which V
cc
is applied to the unselected bit line and the string select transistor SST, V
pgm
is applied to the selected word line, V
pass
is applied to the unselected word lines, and 0V is applied to the selected bit line, the well, and the ground select transistor GST, to thereby self-boost V
pi
to the channels of unselected strings (see, IEEE Journal of Solid State circuits, 1995, pp.1149-1156).
According to the self-boosting scheme, the charge pump capacitor area needed to increase the bit line voltage can be reduced and charging time of the bit line voltage also reduced by applying V
cc
, set to a maximum voltage, to a bit line and only applying a voltage larger than V
cc
to a word line. As a result, chip performance can be enhanced.
A description of a method of self-boosting a channel voltage to inhibit programming of a string cell will be given as follows.
Assuming that a floating gate is set to a neutral state, an average channel voltage (about 7V) in a cell of an unselected bit line is calculated by
V
ch
.
avg
=
(
V
ch
.
sel
+
V
Jang Dong-Soo
Kim Jhang-Rae
Luu C.
Samsung Electronics Co,. Ltd.
Smith Matthew
Volentine & Francos, PLLC
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