WAK devices in SRAM cells for improving VCCMIN

Details WAK devices in SRAM cells for improving VCCMIN WAK devices in SRAM cells for improving VCCMIN

2008-02-20

2010-06-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000

Reexamination Certificate

active

07733687

ABSTRACT:
A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.

REFERENCES:
patent: 2007/0018257 (2007-01-01), Joshi
patent: 2007/0206404 (2007-09-01), Yamagami
patent: 2007/0236983 (2007-10-01), Wang et al.
patent: 2009/0073782 (2009-03-01), Hanafi et al.
Ohbayashi, S., et al., “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability with Read and Write Operation Stabilizing Circuits,” IEEE Journal of Solid-State Circuits, vol. 42, No. 4, Apr. 2007, pp. 820-829, IEEE.
Zhang, K., et al., “A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 146-151, IEEE.

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