Wafer level chip scale package having a gap and method for...

Details Wafer level chip scale package having a gap and method for... Wafer level chip scale package having a gap and method for...

2007-12-25

2007-12-25

Fourson, George R. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S106000, C438S108000, C438S612000, C257S737000, C257S773000, C257S778000

Reexamination Certificate

active

11717691

ABSTRACT:
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

REFERENCES:
patent: 2002/0175409 (2002-11-01), Tsubodaki
patent: 2003/0052156 (2003-03-01), Kim et al.
patent: 2000-228423 (2000-08-01), None
patent: 1020020000692 (2002-01-01), None
patent: 1020030068376 (2003-08-01), None

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