Wafer level chip scale package

Details Wafer level chip scale package Wafer level chip scale package

2007-07-10

2007-07-10

Clark, Jasmine (Department: 2815)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S106000, C438S107000, C438S108000, C438S110000, C438S114000, C438S612000, C438S613000, C438S614000, C438S617000, C438S584000

Reexamination Certificate

active

11126461

ABSTRACT:
A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit film further includes routing conductors that connect inner landings on the bottom surface of the flexible circuit film with outer landings on the top surface of the flexible circuit film. The outer landings are offset a horizontal distance from the inner landings. In some embodiments, contact bumps are formed on the outer landings of the flexible circuit film layer for use in connecting the package to other substrates. The wafer level chip scale package provides a highly compliant connection between the die and any other substrate that the die is attached to.

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