Wafer edge deposition elimination

Details Wafer edge deposition elimination Wafer edge deposition elimination

2000-01-11

2001-05-15

Lund, Jeffrie R. (Department: 1763)

Coating apparatus

Gas or vapor deposition

Having means to expose a portion of a substrate to coating...

C118S728000, C118S729000, C118S715000, C118S500000, C118S504000, C156S345420, C204S298110

Reexamination Certificate

active

06231674

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for depositing useful layers of materials on substrates, for example, semiconductor wafers, used in the manufacture of semiconductor dies. More particularly, this invention relates to a method and apparatus for substantially eliminating unwanted deposition on the edge of the wafer.
2. Background
Overview of Chemical Vapor Deposition
Chemical vapor deposition, commonly referred to as “CVD,” is one of a number of processes used to deposit thin layers of material on a semiconductor wafer, and may be based on thermal, plasma, or optically assisted decomposition, or reaction of chemicals. To process wafers in, for example, a thermal CVD process, a chamber is provided with a susceptor configured to receive a wafer. The wafer is typically placed onto and removed from the susceptor by a robot blade and supported by the susceptor during processing. In these typical systems, the susceptor and the wafer are heated to a temperature of between 200-650° C. prior to processing. Once the wafer is heated to an appropriate temperature, a processing fluid, typically a gas, is introduced into the chamber through a gas manifold often situated above the wafer. The processing gas thermally decomposes upon contact with the heated wafer surface to deposit a thin material layer thereon.
A primary goal of wafer processing is to obtain as many useful die as possible from each wafer. Many factors affect the ultimate yield of die from each wafer processed. These factors include processing variables, which affect the uniformity and thickness of the material layer deposited on the wafer, and particulate contaminants that can attach to a wafer and contaminate one or more die. Both of these factors must be controlled in CVD and other processes to maximize the die yield from each wafer.
Particulate Continuation due to Unwanted Deposition Near the Wafer Edge
One of the causes of particulate contaminants in the chamber is improper deposition at the edge of a wafer. Because edge deposition conditions are difficult to control, due in part to the fact that wafer edges are typically chamfered, incomplete or improper deposition can occur around a wafer's edge. This may lead to deposited layers not adhering properly to each other and/or not adhering properly to the wafer.
This problem is illustrated in FIG.
1
(
a
), which is a schematic partial cross-section of a typical semiconductor wafer. For this example, the wafer
1
is shown with three consecutive deposited layers
2
,
3
, and
4
in which the upper layer
4
is a tungsten layer formed after depositing intermediate layers
2
and
3
(or more layers, if necessary) on the wafer. Such a three-layer process for the deposition of tungsten is common as tungsten does not readily adhere to the silicon (or oxidized silicon) surface of the wafer. Accordingly, the very thin “primer” layer
2
is deposited, followed by the second layer
3
of a material to which tungsten layer
4
readily adheres. As can be seen from FIG.
1
(
a
), however, the tungsten layer
4
has “wrapped” around onto the beveled outer edge
5
of the wafer to come into direct contact with the silicon wafer.
The problem with this wrap around, as described above, is that tungsten does not adhere to the silicon wafer surface and could readily chip and flake during handling of the wafer, resulting in particulate contaminants.
In contrast, FIG.
1
(
b
) illustrates an idealized edge cross-section, in which all three layers terminate at or close to the same point with respect to the wafer's edge, preferably above the chamfer, with the metal layer
4
being the furthest back from the edge of the wafer.
Unwanted Deposition Near the Wafer Edge due to Heating
A factor which affects the uniformity of the deposition material layer is the method used for heating the wafer. One method involves heating the wafer with infared lamps through quartz walls of a reaction chamber. If the heat distribution is non-uniform, the wafer may warp, leading to non-uniform deposition on the top of the wafer as well as unwanted deposition from process gas seeping under upraised portions of the edge of the wafer.
Another method for heating the wafer is to use a heater pedestal for both supporting and heating the wafer. An example of this arrangement is described in the co-pending U.S. patent application Ser. No. 08/200,862 filed on Feb. 23, 1994 and titled “Improved Chemical Vapor Deposition Chamber,” the disclosure of which is hereby incorporated by reference. In this arrangement, the wafer is supported on a flat supporting surface of a heater pedestal mounted on a vertical stalk within the chamber. The pedestal is heated from within by means of an electrical heating coil, and the wafer, in turn, is heated by the hot supporting pedestal. In order to provide improved uniformity of heating of the wafer, the pedestal embodies of a vacuum chuck in which a “vacuum” is drawn at the interface between the underside of the wafer and the flat supporting surface of the pedestal. The resulting pressure differential across the wafer draws the wafer onto the pedestal resulting in improved uniformity of heating of the wafer. But as a result of this vacuum drawn at the backside of the wafer, processing gas can be drawn around the edge of the wafer and into the interface between the wafer and the pedestal. This can result in unwanted edge and backside deposition, leading to the generation of particle contaminants as described earlier. Accordingly, the improved uniformity of heating is accompanied by a possible increase in unwanted edge and backside deposition.
3. Prior Art
A number of prior art solutions to this problem have been proposed:
1. Purge Gas Ring
One solution to the problem of unwanted edge deposition is to use a purge gas ring which defines a manifold between itself and the heater body. During processing, a purge fluid, such as a gas, is injected through the heater body into the manifold and is projected toward the edge of the wafer at the outlet of the manifold. Consequently, processing gas is inhibited from contacting the extreme edge portion of the wafer. This method theoretically reduces unwanted deposition on the peripheral edge and lower surface of the wafer to produce the deposit pattern shown in FIG.
1
(
b
). In practice, however, the purge gas ring is not as successful as might be desired.
2. Shadow Ring
Another solution to this problem is to provide a shadow ring which is located over and in contact with a narrow peripheral area of the wafer to prevent deposition thereon. As shown in FIG.
1
(
c
), use of the shadow ring provides an undeposited annular strip around the wafer edge, which is sometimes desirable from a wafer handling perspective. However, the shadow ring is also not as successful as might be desired because of wafer warpage and the fact that the volatile deposition gas still tends to migrate under the lip of the shadow ring and deposit unwanted material on the wafer edge and backside. Furthermore, any misalignment of the shadow ring with respect to the wafer may result in incomplete shadowing of the wafer edge.
The need therefore exists for a method and apparatus for controlling the deposition of materials at or around the edge of a semiconductor wafer during CVD and/or other wafer processing operations.
SUMMARY OF THE INVENTION
This invention provides a method and apparatus for masking the edge of a wafer supported on a substrate support, such as a heater pedestal, in a processing chamber. Process fluid, such as a gas, is flowed onto the wafer surface, and is inhibited from depositing near the wafer edge by a shadow ring placed over but not in contact with the wafer. The shadow ring defines a wafer edge circumscribing cavity into which purge gas is flowed. This purge gas flows out from the cavity through the gap between the shadow ring and the upper surface of the wafer.
Thus, the shadow ring inhibits deposition of process gases on the wafer in two distinct ways. First, the shadow ring physically ob

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