Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-02-27
2000-06-27
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438636, 438638, 438640, 438672, 438739, 257751, 257764, 257770, H01L 214763
Patent
active
060806605
ABSTRACT:
A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.
REFERENCES:
patent: 3858231 (1974-12-01), Magdo et al.
patent: 5756396 (1998-05-01), Lee et al.
patent: 5811353 (1998-09-01), Nanjo
patent: 5827778 (1998-10-01), Yamada
patent: 5888901 (1999-03-01), Grivna
Chou Hsiao-Pang
Hsieh Wen-Yi
Wang Kun-Chih
Yew Tri-Rung
Nguyen Ha Tran
Niebling John F.
United Microelectronics Corp.
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