Methods for fabricating gate and diffusion contacts in self-alig

Details Methods for fabricating gate and diffusion contacts in self-alig Methods for fabricating gate and diffusion contacts in self-alig

1998-05-29

2000-06-27

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438233, 438634, 438702, H01L 214763

Patent

active

060806613

ABSTRACT:
Disclosed are methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer. The semiconductor device includes a plurality of transistor devices having diffusion regions and polysilicon gate electrodes, and an oxide material that covers a top surface of the polysilicon gate electrodes of the transistor devices. A silicon nitride layer is also disposed over the semiconductor devices and a dielectric layer is disposed over the silicon nitride layer. The method includes depositing a silicon nitride layer over the dielectric layer, and etching nitride windows in the silicon nitride layer to expose the dielectric layer where conductive contacts to selected polysilicon gate electrodes are desired. The method then includes pattering a photoresist mask over the silicon nitride layer. The photoresist mask is configured to have a plurality of windows defining all contacts to both selected ones of the diffusion regions and selected ones of the polysilicon gate electrodes, and some of the plurality of windows are defined over the nitride windows. Furthermore, the method includes performing a series of dielectric and silicon nitride etch operations to substantially simultaneously form via holes down to selected polysilicon gate electrodes and selected diffusion regions. Once the via holes are etched, a suitable conductive contact fill process may be performed.

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