Vertical transistor structure for use in semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S330000, C257S332000, C257S520000, C257SE29201

Reexamination Certificate

active

07408224

ABSTRACT:
According to some embodiments, a structure of vertical transistor includes gate electrodes distanced by a predetermined interval in an active region, formed in a vertical shape to have a predetermined depth from a top surface of a semiconductor substrate. A gate insulation layer is formed between one side wall of the gate electrode and the substrate. A gate spacer is formed in another sidewall of the gate electrode, covering the gate electrode. A contact plug is formed between the gate spacer. A plug impurity layer is formed in a lower part of the contact plug, and source and drain are formed opposite to the gate electrode within the active region. Thereby, an area occupied by a gate electrode is substantially reduced, so a unit memory cell has a 4F2structure, reducing a memory cell size, by forming a vertical-type gate electrode within an active region.

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