Vertical SOI trench SONOS cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29309

Reexamination Certificate

active

07893485

ABSTRACT:
A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

REFERENCES:
patent: 5424569 (1995-06-01), Prall
patent: 5459083 (1995-10-01), Subrahmanyan et al.
patent: 5480832 (1996-01-01), Miura et al.
patent: 6787419 (2004-09-01), Chen et al.
patent: 6954921 (2005-10-01), Hassibi et al.
patent: 2005/0145921 (2005-07-01), Chang et al.
Swift, et al., “An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase,” IEDM Tech. Dig., Dec. 2002, pp. 927-930.
U.S. Appl. No. 11/164,513, entitled “Vertical SOI Trench SONOS Cell” filed Nov. 28, 2005, First Named Inventor: David Dobuzinsky.

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