Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-04
2002-04-23
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S138000, C438S273000, C438S212000
Reexamination Certificate
active
06376311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a vertical double diffused MOSFET and method for manufacturing same, and more particularly to a vertical double diffused MOSFET manufactured through a self-aligned process which is applicable for switching power sources, AC adapters, battery chargers, motor control circuits, inverter illumination, DC/DC converters or the like, and a method for manufacturing such a device.
2. Description of the Prior Art
There is shown in
FIG. 3
a conventional vertical double diffused MOSFET of the kind as above. The MOSFET
1
includes a semiconductor substrate
2
having a main body
2
a
and an epitaxial layer
2
b.
The semiconductor substrate
2
has a main diffusion region
3
a
formed in a surface thereof. The semiconductor substrate
2
has, on the surface, a gate electrode
5
having at least one window
5
a
formed through an oxide film
4
. The semiconductor substrate
2
is formed, at its bottom surface, with a drain electrode
6
. Also, in the surface of the semiconductor substrate
2
, a channel diffusion region
3
b
and source diffusion region
3
c
is formed in relation to the gate electrode
5
at a peripheral edge of the window
5
a.
On the gate electrode
5
an insulation layer
7
is formed of oxide silicon containing phosphorus (PSG). Over the insulation layer
7
, a metal interconnect layer (source electrode)
8
is formed connecting to a source diffusion region
3
c.
In manufacturing a vertical double diffused MOSFET
1
, an n-type epitaxial layer
2
b
and oxide film
9
a
is formed on an n-type semiconductor substrate (main body)
2
a,
as shown in FIG.
4
A. The oxide film
9
a
at one part is removed by etching to form a window
9
b.
Through this window
9
b
boron (B) ions are implanted to the surface of the semiconductor substrate
2
. After etch-removing oxide film
9
a,
the boron (B) ions are thermally diffused to thereby provide a main diffusion region
3
a.
Simultaneous with this, a not-shown thermal oxide film is formed. As shown in
FIG. 4B
, this thermal oxide film is etched under a predetermined condition into an oxide film
4
having a thick walled portion
9
c.
Subsequently, as shown in
FIG. 4C
a gate electrode
5
is formed on the oxide film
4
, and part of the gate electrode is etched to thereby provide a window
5
a.
Then, boron (B) ions are implanted through, as a mask, the gate electrode
5
into the surface of the semiconductor substrate
2
. The implanted boron ions are thermally diffused to form a channel diffusion region
3
b.
Further, phosphorus (P) ions are implanted through, as a mask, the gate electrode
5
and thick walled portion
9
c
to the surface of the semiconductor substrate
2
. The implanted phosphorus ions are then thermally diffused to provide a source diffusion
3
c.
Then an insulation layer
7
is formed over the oxide film
4
and gate electrode
5
, as shown in FIG.
4
E. Subsequently, as shown in
FIG. 4F
, the insulation layer
7
and oxide film
4
is partly etched away to form a contact hole
9
d.
Thereafter, a metal interconnect layer
8
is formed on the insulation layer
7
in a manner of connected to the source diffusion region
3
c,
as shown in FIG.
3
. Further, a drain electrode
6
is formed at the underside of the semiconductor substrate
2
.
In the prior art, however, the insulation layer
7
has used silicon oxide containing phosphorus (PSG). Therefore, it has been impossible to completely block contaminants, such as mobile ions, from intruding into the electrode
5
during the manufacture process or in an operational environment after manufacture. Due to this, there has been a problem that the gate electrode
5
deteriorate in electric characteristic (threshold voltage, etc) due to aging.
On the other hand, the thick walled portion
9
c
was formed in a separate process (
FIG. 4B
) from the process of forming the main diffusion region
3
a
(FIG.
4
A), making the manufacture process complicated. Moreover, there existed a fear that misalighnment might occur in each of the processes. If a misalignment be caused in the process of forming the thick walled portion
9
c,
the source diffusion regions
3
c
on left and right of the thick walled portion
9
c
were formed into different widths from each other. Thus, there has been a fear of causing variation in electric current amount to be supplied to these source diffusion regions
3
c
from the metal interconnect layer
8
.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of the present invention to provide a vertical double diffused MOSFET which is capable of preventing the gate electrode from deteriorating in its characteristic, and a method for manufacturing such a device.
It is another object of the present invention to provide a method for manufacturing a vertical double diffused MOSFET wherein the process that might lead to misalignment is eliminated thus stabilizing product quality.
A vertical double diffused MOSFET according to the present invention is characterized in that a nitride film is used as an insulation layer interposed between a gate electrode and a metal interconnect layer.
That is, a vertical double diffused MOSFET, comprises: a semiconductor substrate; an oxide film formed on the semiconductor substrate; a gate electrode formed on the oxide film and having at least one window; a nitride film formed on the oxide film and the gate electrode; an ion implant window formed through the nitride film at a center of the window, ions of a first conductivity type being implanted through the ion implant window to the semiconductor substrate and thermally diffused thereby forming a main diffusion region; a thick walled portion formed by growing the oxide film in the ion implant window, wherein ions of the first conductivity type are implanted through as a mask the gate electrode and the nitride film on the gate electrode into the semiconductor substrate and thermally diffused to form a channel diffusion region, and ions of a second conductivity type being implanted through as a mask the thick walled portion, the gate electrode and the nitride film on the gate electrode into the semiconductor substrate and thermally diffused thereby forming a source diffusion region.
A method for manufacturing a vertical double diffused MOSFET according to the present invention, comprises the steps of: (a) forming an oxide film on a substrate; (b) forming a gate electrode having at least one window on the oxide film; (c) forming a nitride film as an insulation layer on the oxide film and the gate electrode; (d) forming an ion implant window through the nitride film at a center of the window; (e) implanting ions of a first conductivity type through the ion implant window to the substrate; (f) thermally diffusing the ions to form a main diffusion region and growing the oxide film inside the ion implant window to form a thick walled portion; (g) implanting ions of the first conductivity type through as a mask the thick walled portion, the gate electrode and the nitride film on the gate electrode to the substrate and thermally diffusing to form a channel diffusion region; and (h) implanting ions of a second conductivity type through a mask of the thick walled portion, the gate electrode and the nitride film on the gate electrode to the substrate and thermally diffusing to form a source diffusion region.
In the vertical double diffused MOSFET according to the present invention, the nitride film interposed between the gate electrode and the metal interconnect layer has a dense film texture. This nitride film serves to physically shield contaminants from entering into the gate electrode. Consequently, the gate electrode is prevented from deteriorating in characteristic due to contaminants.
Furthermore, in the manufacture method, the main diffusion region and the thick walled portion are simultaneously formed in the step (f). This reduces the number of processes leading to misalignment as compared to the prior art of
FIG. 4
wherein these formations are carried out by differen
Hoffman & Baron LLP
Jr. Carl Whitehead
Rohm & Co., Ltd.
Vockrodt Jeff
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