Variable clocked scan test circuitry and method

Details Variable clocked scan test circuitry and method Variable clocked scan test circuitry and method

2007-06-19

2007-06-19

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000

Reexamination Certificate

active

10351276

ABSTRACT:
A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.

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